Title: Digital Integrated Circuits A Design Perspective
1Digital Integrated CircuitsA Design Perspective
ManufacturingProcess
July 30, 2002
2CMOS Process
3A Modern CMOS Process
Dual-Well Trench-Isolated CMOS Process
4Circuit Under Design Layout View
5Photo-Lithographic Process
optical
mask
oxidation
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
6Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
(b) After oxidation and deposition
SiO
of negative photoresist
2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
7CMOS Process at a Glance
8CMOS Process Walk-Through
9CMOS Process Walk-Through
10CMOS Process Walk-Through
11CMOS Process Walk-Through
12Advanced Metallization
- Introduced by IBM
- Filling trench, then polishing
13Design Rules
143D Perspective
Polysilicon
Aluminum
15Design Rules
- Interface between designer and process engineer
- Guidelines for constructing process masks
- Unit dimension Minimum line width
- scalable design rules lambda parameter
- absolute dimensions (micron rules)
16CMOS Process Layers
17Layers in 0.25 mm CMOS process
18Intra-Layer Design Rules
4
Metal2
3
19Transistor Layout
20Vias and Contacts
21CMOS Inverter Layout
22Layout Editor
23Design Rule Checker
poly_not_fet to all_diff minimum spacing 0.14
um.
24Sticks Diagram
- Dimensionless layout entities
- Only topology is important
- Final layout generated by compaction program
25Packaging
26Packaging Requirements
- Electrical Low parasitics
- Mechanical Reliable and robust
- Thermal Efficient heat removal
- Economical Cheap
27Die-to-Package Wire Bonding
28Die-to-Package Tape-Automated Bonding (TAB)
29Die-to-Package Flip-Chip Bonding
30Package-to-Board
31Package Types
- Bare die
- DIP
- PGA
- Small-outline IC
- QFP
- PLCC (J-shaped)
- Leadless carrier
32Package Parameters
33Multi-Chip Modules
- R, C, L parasitic reduced
- But, cost increased