Digital Integrated Circuits A Design Perspective

1
Digital Integrated CircuitsA Design Perspective
ManufacturingProcess
July 30, 2002
2
CMOS Process
3
A Modern CMOS Process
Dual-Well Trench-Isolated CMOS Process
4
Circuit Under Design Layout View
5
Photo-Lithographic Process
optical
mask
oxidation
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
6
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
(b) After oxidation and deposition
SiO
of negative photoresist
2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
7
CMOS Process at a Glance
8
CMOS Process Walk-Through
9
CMOS Process Walk-Through
10
CMOS Process Walk-Through
11
CMOS Process Walk-Through
12
Advanced Metallization

• Introduced by IBM
• Filling trench, then polishing

13
Design Rules
14
3D Perspective
Polysilicon
Aluminum
15
Design Rules

• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension Minimum line width
• scalable design rules lambda parameter
• absolute dimensions (micron rules)

16
CMOS Process Layers
17
Layers in 0.25 mm CMOS process
18
Intra-Layer Design Rules
4
Metal2
3
19
Transistor Layout
20
Vias and Contacts
21
CMOS Inverter Layout
22
Layout Editor
23
Design Rule Checker
poly_not_fet to all_diff minimum spacing 0.14
um.
24
Sticks Diagram

• Dimensionless layout entities
• Only topology is important
• Final layout generated by compaction program

25
Packaging
26
Packaging Requirements

• Electrical Low parasitics
• Mechanical Reliable and robust
• Thermal Efficient heat removal
• Economical Cheap

27
Die-to-Package Wire Bonding
28
Die-to-Package Tape-Automated Bonding (TAB)
29
Die-to-Package Flip-Chip Bonding
30
Package-to-Board
31
Package Types

• Bare die
• DIP
• PGA
• Small-outline IC
• QFP
• PLCC (J-shaped)
• Leadless carrier

32
Package Parameters
33
Multi-Chip Modules

• R, C, L parasitic reduced
• But, cost increased