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Digital Integrated Circuits A Design Perspective

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Title: Digital Integrated Circuits A Design Perspective


1
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Arithmetic Circuits
2
A Generic Digital Processor
3
Building Blocks for Digital Architectures
Arithmetic unit

Bit-sliced datapath
(adder, multiplier, shifter, comparator, etc.)
-
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
4

Arithmetic building blocks
  • Speed and power of arithmetic components often
    dominates the overall system performance
  • For each module, multiple topologies and ways
    exists, with each of them has its own advantages
  • A global picture is of crucial importance. A
    designer focus their attention on gates or
    transistors that have the largest impact on their
    goal function. Non-critical components can be
    developed routinely.
  • Typically two optimization process logic
    optimization (re-arrange Boolean equations so
    that a faster or small circuit could be obtained)
    circuit optimization (manipulate transistor sizes
    and circuit topology to optimize speed)

5
Bit-Sliced Design
Since the same operation has to be performed on
each bit of data word, the data path can consist
of the number of bit slices (equal to the word
length), each operating on a single bit hence
the term bit-sliced
6
Adders
7
Full-Adder
8
The Binary Adder
9
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) AB
Propagate (P) A
B
Å
Delete
A

B
S
C
D and P
Can also derive expressions for
and
based on

o
Note that we will be sometimes using an alternate
definition for

Propagate (P) A
B
10
The Ripple-Carry Adder
Worst case delay linear with the number of bits
td O(N)
tadder (N-1)tcarry tsum
Goal Make the fastest possible carry path circuit
11
Complimentary Static CMOS Full Adder
28 Transistors
12
Complimentary Static CMOS Full Adder
Large PMOS stacks are present in both carry and
sum generation circuits Intrinsic load
capacitance of Co signal is large and consists of
eight capacitance components There is one more
inverter delay for carry and sum (worse when the
load capacitance is large) Note that critical
signal Ci closer to the output node
13
Inversion Property
14
Minimize Critical Path by Reducing Inverting
Stages
Exploit Inversion Property
15
Transmission Gate XOR
When B1, M1/M2 inverter, M3/M4 off, so FAB When
B0, M1/M2 off, M3/M4 transmission gate, so FAB
16
Transmission Gate Full Adder
17
Manchester Carry Chain
Generate (G) AB
Propagate (P) A
B
Å
Delete
A

B
18
Full-Adder
19
Manchester Carry Chain
20
Manchester Carry Chain
Stick Diagram
21
Manchester Carry Chain
  • Delay for the Manchester Carry Chain can be
    modeled similar to the a linearized RC network as
    in transmission-gates
  • This means the propagation delay is quadratic in
    the number of bits N. (but does not imply the
    delay will be larger than the ripple carry adder)
  • It might be necessary to insert signal buffering
    inverters.
  • Still a ripple carry adder, typically only good
    for small word length (lt8/16 bits)
  • We need faster adders for computer and
    multimedia applications with word length 32-128
    bits

22
Carry-Bypass Adder
Also called Carry-Skip
Break the bit-slice organization
23
Carry-Bypass Adder (cont.)
tadder tsetup Mtcarry (N/M-1)tbypass
(M-1)tcarry tsum
(worst case)
Tsetup overhead time to create G, P, D signals
24
Carry Ripple versus Carry Bypass
25
Carry-Select Adder
26
Carry Select Adder Critical Path
27
Linear Carry Select
28
Square Root Carry Select
M
29
Adder Delays - Comparison
Bypass
30
LookAhead - Basic Idea
31
Look-Ahead Topology
Expanding Lookahead equations
All the way
32
Logarithmic Look-Ahead Adder
33
Carry Lookahead Trees
Can continue building the tree hierarchically.
34
Tree Adders
16-bit radix-2 Kogge-Stone tree
35
Tree Adders
16-bit radix-4 Kogge-Stone Tree
36
Sparse Trees
16-bit radix-2 sparse tree with sparseness of 2
37
Tree Adders
Brent-Kung Tree
38
Example Domino Adder
Propagate
Generate
39
Example Domino Adder
Propagate
Generate
40
Example Domino Sum
41
Intel Itanium Microprocessor
Itanium has 6 integer execution units like this
42
Bit-Sliced Design
43
Bit-Sliced Datapath
The adder is implemented as a radix-4 Carry
look-ahead adder, the red lines are forwarding
the results of different stages
44
Itanium Integer Datapath
Courtesy of Intel
45
Multipliers
46
The Binary Multiplication
47
The Binary Multiplication
48
The Array Multiplier (4 by 4)
Half adder
carry
sum
The carryout of the last adder for Yi is
forwarded to Yi1
49
The MxN Array Multiplier Critical Path
Critical Path 1 2
50
Carry-Save Multiplier
A more efficient realization can be obtained by
noticing that the multiplication results does not
change when the output carry bits are passed
diagonally downwards instead of to the right.
But need extra adders (vector merging adders)
that can use fast carry look ahead adders (same
time) Critical path is uniquely defined
51
Multiplier Floorplan
52
Wallace-Tree Multiplier
Save the number of full adders Increase the
complexity of routing
53
Wallace-Tree Multiplier
HA
Can use carry lookahead adder for last stage
54
Wallace-Tree Multiplier
55
Booth encoding
  • Multiply by 01111110 gives 8 partial products,
    but two are all zero. Add these zero is waste of
    time.
  • Instead, multiply by 100000010, where 1 stands
    for -1. Then you need to only add (actually
    subtract) partial products, which improves speed
  • This kind of transformation is called booth
    encoding. It reduces the number of partial
    product to at most half of the original
    multiplier width.
  • The encoding logic is easily incorporated in the
    overall multiplier design.

56
Multipliers Summary
57
Shifters
58
The Binary Shifter
59
The Barrel Shifter
Column maximum shift
Word length
Area Dominated by Wiring
Signal pass through one gate independent of shift
amount
60
4x4 barrel shifter
Coder/decoder required to set shift bits
61
Logarithmic Shifter
62
0-7 bit Logarithmic Shifter
A
3
Out3
A
2
Out2
A
1
Out1
A
0
Out0
Good for large shift amount (note that cascade
pass transistor slow down the gate and generate
weak signals)
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