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Digital Integrated Circuits A Design Perspective

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Digital Integrated Circuits A Design Perspective Arithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, Anantha Chandrakasan and ... – PowerPoint PPT presentation

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Title: Digital Integrated Circuits A Design Perspective


1
Digital Integrated Circuits A Design Perspective
Arithmetic Circuits
Reference Digital Integrated Circuits, 2nd
edition, Jan M. Rabaey, Anantha Chandrakasan and
Borivoje Nikolic Disclaimer slides adapted for
INE5442/EEL7312 by José L. Güntzel from the
books companion slides made available by the
authors.
2
A Generic Digital Processor
3
Building Blocks for Digital Architectures
Arithmetic unit

Bit-sliced datapath
(adder, multiplier, shifter, comparator, etc.)
-
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
4
An Intel Microprocessor
Itanium has 6 integer execution units like this
5
Bit-Sliced Design
6
Bit-Sliced Datapath
7
Itanium Integer Datapath
Fetzer, Orton, ISSCC02
8
Adders
9
Full-Adder
10
The Binary Adder
11
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) AB
Propagate (P) A
B
Å
Delete
A

B
S
C
D and P
Can also derive expressions for
and
based on

o
Note that we will be sometimes using an alternate
definition for

Propagate (P) A
B
12
The Ripple-Carry Adder
Worst case delay linear with the number of bits
td O(N)
tadder (N-1)tcarry tsum
Goal Make the fastest possible carry path circuit
13
Complimentary Static CMOS Full Adder
28 Transistors
14
Inversion Property
15
Minimize Critical Path by Reducing Inverting
Stages
Exploit Inversion Property
16
A Better Structure The Mirror Adder
17
Mirror Adder
Stick Diagram
18
The Mirror Adder
  • The NMOS and PMOS chains are completely
    symmetrical. A maximum of two series transistors
    can be observed in the carry-generation
    circuitry.
  • When laying out the cell, the most critical issue
    is the minimization of the capacitance at node
    Co. The reduction of the diffusion capacitances
    is particularly important.
  • The capacitance at node Co is composed of four
    diffusion capacitances, two internal gate
    capacitances, and six gate capacitances in the
    connecting adder cell .
  • The transistors connected to Ci are placed
    closest to the output.
  • Only the transistors in the carry stage have to
    be optimized for optimal speed. All transistors
    in the sum stage can be minimal size.

19
Transmission Gate Full Adder
20
Manchester Carry Chain
21
Manchester Carry Chain
22
Manchester Carry Chain
Stick Diagram
23
Carry-Bypass Adder
Also called Carry-Skip
24
Carry-Bypass Adder (cont.)
tadder tsetup Mtcarry (N/M-1)tbypass
(M-1)tcarry tsum
25
Multipliers
26
The Binary Multiplication
27
The Binary Multiplication
28
The Array Multiplier
29
The MxN Array Multiplier Critical Path
Critical Path 1 2
30
Carry-Save Multiplier
31
Multiplier Floorplan
32
Shifters
33
The Binary Shifter
34
The Barrel Shifter
Area Dominated by Wiring
35
4x4 barrel shifter
Widthbarrel 2 pm M
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