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Digital Integrated Circuits A Design Perspective

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... Domino Sum Multipliers The Binary Multiplication The Binary Multiplication The Array Multiplier The MxN Array Multiplier Critical Path Carry-Save ... – PowerPoint PPT presentation

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Title: Digital Integrated Circuits A Design Perspective


1
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Arithmetic Circuits
January, 2003
2
A Generic Digital Processor
3
Building Blocks for Digital Architectures
Arithmetic unit

Bit-sliced datapath
(adder, multiplier, shifter, comparator, etc.)
-
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
4
An Intel Microprocessor
Itanium has 6 integer execution units like this
5
Bit-Sliced Design
6
Bit-Sliced Datapath
7
Itanium Integer Datapath
Fetzer, Orton, ISSCC02
8
Adders
9
Full-Adder
10
The Binary Adder
11
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) AB
Propagate (P) A
B
Å
Delete
A

B
S
C
D and P
Can also derive expressions for
and
based on

o
Note that we will be sometimes using an alternate
definition for

Propagate (P) A
B
12
The Ripple-Carry Adder
Worst case delay linear with the number of bits
td O(N)
tadder (N-1)tcarry tsum
Goal Make the fastest possible carry path circuit
13
Complimentary Static CMOS Full Adder
28 Transistors
14
Inversion Property
15
Minimize Critical Path by Reducing Inverting
Stages
Exploit Inversion Property
16
A Better Structure The Mirror Adder
17
Mirror Adder
Stick Diagram
18
The Mirror Adder
  • The NMOS and PMOS chains are completely
    symmetrical. A maximum of two series transistors
    can be observed in the carry-generation
    circuitry.
  • When laying out the cell, the most critical issue
    is the minimization of the capacitance at node
    Co. The reduction of the diffusion capacitances
    is particularly important.
  • The capacitance at node Co is composed of four
    diffusion capacitances, two internal gate
    capacitances, and six gate capacitances in the
    connecting adder cell .
  • The transistors connected to Ci are placed
    closest to the output.
  • Only the transistors in the carry stage have to
    be optimized for optimal speed. All transistors
    in the sum stage can be minimal size.

19
Transmission Gate Full Adder
20
Manchester Carry Chain
21
Manchester Carry Chain
22
Manchester Carry Chain
Stick Diagram
23
Carry-Bypass Adder
Also called Carry-Skip
24
Carry-Bypass Adder (cont.)
tadder tsetup Mtcarry (N/M-1)tbypass
(M-1)tcarry tsum
25
Carry Ripple versus Carry Bypass
26
Carry-Select Adder
27
Carry Select Adder Critical Path
28
Linear Carry Select
29
Square Root Carry Select
30
Adder Delays - Comparison
31
LookAhead - Basic Idea
32
Look-Ahead Topology
Expanding Lookahead equations
All the way
33
Logarithmic Look-Ahead Adder
34
Carry Lookahead Trees
Can continue building the tree hierarchically.
35
Tree Adders
16-bit radix-2 Kogge-Stone tree
36
Tree Adders
16-bit radix-4 Kogge-Stone Tree
37
Sparse Trees
16-bit radix-2 sparse tree with sparseness of 2
38
Tree Adders
Brent-Kung Tree
39
Example Domino Adder
Propagate
Generate
40
Example Domino Adder
Propagate
Generate
41
Example Domino Sum
42
Multipliers
43
The Binary Multiplication
44
The Binary Multiplication
45
The Array Multiplier
46
The MxN Array Multiplier Critical Path
Critical Path 1 2
47
Carry-Save Multiplier
48
Multiplier Floorplan
49
Wallace-Tree Multiplier
50
Wallace-Tree Multiplier
51
Wallace-Tree Multiplier
52
Multipliers Summary
53
Shifters
54
The Binary Shifter
55
The Barrel Shifter
Area Dominated by Wiring
56
4x4 barrel shifter
Widthbarrel 2 pm M
57
Logarithmic Shifter
58
0-7 bit Logarithmic Shifter
A
3
Out3
A
2
Out2
A
1
Out1
A
0
Out0
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