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Digital Integrated Circuits A Design Perspective

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Implant source and drain. regions and substrate contacts. Create contact and via windows ... source/drain implants. These. p. n. steps also dope the polysilicon. ... – PowerPoint PPT presentation

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Title: Digital Integrated Circuits A Design Perspective


1
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Manufacturing Process
July 30, 2002
2
CMOS Process
3
A Modern CMOS Process
Dual-Well Trench-Isolated CMOS Process
4
Circuit Under Design
5
Its Layout View
6
The Manufacturing Process
For a great simplified tour through an IC
foundary, check http//www.necel.com/v_factory/en/
index.html
7
Photo-Lithographic Process
optical
mask
oxidation
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
8
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
(b) After oxidation and deposition
SiO
of negative photoresist
2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
9
CMOS Process at a Glance
10
CMOS Process Walk-Through
11
CMOS Process Walk-Through
12
CMOS Process Walk-Through
13
CMOS Process Walk-Through
14
Metallization
15
Design Rules
16
3D Perspective
Polysilicon
Aluminum
17
Design Rules
  • Interface between designer and process engineer
  • Guidelines for constructing process masks
  • Unit dimension Minimum line width
  • scalable design rules lambda parameter
  • absolute dimensions (micron rules)

18
CMOS Process Layers
19
Layers in 0.25 mm CMOS process
20
Intra-Layer Design Rules
4
Metal2
3
21
Transistor Layout
22
Vias and Contacts
23
Select Layer
24
CMOS Inverter Layout
25
Layout Editor
26
Design Rule Checker
poly_not_fet to all_diff minimum spacing 0.14
um.
27
Sticks Diagram
  • Dimensionless layout entities
  • Only topology is important
  • Final layout generated by compaction program

28
Packaging
Interface between silicon and the outside world
29
Packaging Requirements
  • Electrical Low parasitics
  • Mechanical Reliable and robust
  • Thermal Efficient heat removal
  • Economical Cheap

30
Bonding Techniques
31
Tape-Automated Bonding (TAB)
32
Flip-Chip Bonding
33
Package-to-Board Interconnect
34
Package Types
35
Package Parameters
36
Multi-Chip Modules
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