Chip Packaging 2'0 UserDefinable Pinout' Enabling board designers to define wire bonding schedules'

1
Chip Packaging 2.0User-Definable
Pinout.Enabling board designers to define wire
bonding schedules.
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Customers Unmet Need

• Chip Packaging 1.0

Design teams dont talk.
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Current Chip Packaging 1.0 Prevents
optimized board design

• Chip pinouts defined in data sheets, by silicon
  team

• Boards getting complex, with 1224 layers

• Board design cycles are getting longer,
  with more
  spins to optimize design

• Board designers start out of the gate with their
  shoe laces tied together - failing to design
  Optimum boards

There should be a better way
and there is!
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Chip Packaging 2.0

• What if ?

What if legacy chips could be User-Definable
Pinouts (UDPo)?

• This would allow system customers to
• Design smaller, lighter systems with fewer
  layers, higher
  performance, quicker to market and lower cost

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Re-mapping pair-of-pins,
simplifies the board
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Systems become simpler in Chip Packaging
2.0 world
Example of point-to-point board routing With UDPo
(User-Definable Pinout)
Single layer board
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Insulated Bonding Wires Secret Sauce

• Insulated wires make UDPo
  user definable pinouts feasible.

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Chip Packaging 2.0 Benefits

• Opportunities for legacy chips
• Not dependent on Moores Law
• UDPo advantages
• Smaller boards lighter systems
• Simpler boards - reduced complexity
• Quicker time to market competitive advantage
• Higher performancefaster speed
• Less raw materials cost savings

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Systems cost soars as complexity rises

• What if UDPo could reduce a 14 layer board to 8
  layers?

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Additional cost of UDPo user-definable

compared to legacy chip packaging

• IC packaging average price

UDPo becomes more economical as unit volume
increases.
100
UDPo User-Definable Pinout
50 more
50
15 more
20
Legacy Chip
10 more
UDPo approaches parity 3
10
0
1K 10K 100K 1M
10M 100M
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Saving per assembly
with UDPo
User Definable Pinout chips

• Percentage Savings per Assembly

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Target Customer Market

• OEM System producers
• OEM Cisco, Broadcom, HP, RadiSys, etc
• EMS Flextronics, Celestica, Foxconn, Sanmina,
  others
• IDM Fabless Chip Makers

• Markets
• Consumer products
• Industrial products
• Defense

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Team - Whos Involved

• Technology Partners Hestia
  Verdant Electronics
  Microbonds
  Promex
  Liberty University
  CAD Design Software
• Marketing Partner TopLine, others
• EDA Partners CAD Design Software other
  Developers of Cadence, Mentor Graphics PCB
  software, others

• Advisory Board
• Dr. Gerald "Skip" Fehr 35 years IC Packaging.
  PhD in Ceramic Engineering.
• Pankaj Gulati - 25 years manufacturing
  semiconductors. Masters degree in physics.
• Bert Haskell - 20 years technology experience in
  packaging technologies. Accomplished author.
• Patrick Weber 30 years experience in
  semiconductor packaging. Holds 19 patents. CEO of
  Hestia.
• Joseph Fjelstad - 34-year veteran of electronics
  interconnection industry. 120 issued patents. CEO
  Verdant Electronics.
•  
• Naeem Zafar - Serial entrepreneur. Devoted to
  mentorship. Partner with Concordia Ventures.
  Masters electrical engineering.
• Dr. Ken Gilleo - 35 years packaging experience.
  33 patents. PhD in chemistry.

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Progress-to-Date Road Map Milestones
Production
Beta
Progress to Date
Q4-06
H1-07
2H-08
1H-08
1H09
2H09
H2-07
Mirrored Pinout concept
Proof of Concept Demo
Qualifications Samples
Prototype Package Produced
Deliver Production Quantities
Company founded. Select advisory board.
EDA Software Pinout Optimization and PCB
Autorouting
2 patent applications.
Chip Packaging 2.0 UDPo
User Definable Pinouts
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Challenges / Opportunities - UDPo

• The Challenges
• Signal integrity - cross talk modeling with
  multiple crossovers
• Testing issues how and when to test?
• Height of crossing wires may exceed package
  headroom limit
• Supply esprit de corps cooperativeness
  availability die/wafers
• EDA Software autorouting/algorithms - Library
  of constraints.
• Market Acceptance identifying and educating
  customers

The Opportunity UDPo has significant and
compelling benefits. The design community must
rally and address formidable challenges to
overcome constraints and gain greater freedoms
that UDPo offers.
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Company Info

• Martin Hart Founder
• CEO of start up Mirror Semi Chip packaging and
  board optimization EDA software products
• 15 years CEO of TopLine - Chip packaging test
  vehicle board supplier
• 20 years Marketing distribution of electronic
  components CEO of
  National Electronics
• First hand involvement designing PCB boards
• Provided hundreds of chip packaging solutions to
  customers
• Mirror Semiconductor, Inc.
• Irvine, California
• Contact Martin Hart [phone]
  Hart_at_MirrorSemi.com

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Contact

• AnyChipTM MirrorChipTM
• StackChipTM

Mirror Semiconductor, Inc. 17595 Harvard Ave.,
Suite 509 Irvine, California 92614 USA Tel
1-949-250-4001 Email hart_at_MirrorSemi.com Web
www.MirrorSemi.com Contact Martin Hart,
President