ECE 444

1
ECE 444

• Session 4
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_who.rr.com

2
Modular Approach

• The Ripple Carry Adder designs illustrate the
  modular approach supported by Verilog
• Once a module has been defined, it can be
  instantiated in another module
• The Quartus compiler looks for the modules in the
  project directory
• Other compilers may require you to have the
  module definition included in the file (like a
  subroutine)

3
Notes on Adders

• Ripple Adder add time is proportional to the
  number of bits in the adder
• Theoretical Limit is two gate delays which should
  be on the order of our full adder implementation
  time delays
• This limit is not realizable since the number of
  inputs required for each gate grows with the
  number of bits desired in the adder.
• A typical maximum fan-in is 8 inputs
• Faster adders may be built using parallel rather
  than ripple carry techniques

4
Carry Look-ahead Adder

• Recall the truth table for the full adder module

Carry Propagate
Carry Propagate
Carry Generate
Carry Generate
5
Carry Generate and Propagate

• The rows labeled Carry Generate cause a carry out
  from the stage independent of the carry in
• The rows labeled Carry Propagate cause the carry
  out to match the carry in
• From the truth table, we can define the following
  equations
• The sum and carry out from the stage can be
  expressed as follows

Pi Ai ? Bi and, Gi Ai Bi
Si Pi ? Ci and, Ci1 Gi Pi Ci
6
Carry Equations

• The Boolean equations for each output carry can
  now be written recursively from the carry
  equation on the previous chart (switching to
  Verilog Style Notation
• Since the Boolean function for each carry is
  expressed in a sum of products form, it can be
  implemented by two levels of gates

C0 carry in C1 G0 P0 C0 C2
G1 P1 C1 G1 P1 G0
P1 P0 C0 C3 G2 P2 C2
G2 P2 G1 P2 P1 G0
P2 P1 P0 C0 C4 carry out
G3 P3 G2 P3 P2 G1
P3 P2 P1 G0 P3 P2
P1 P0 C0
7
Carry Look-ahead Adder
8
Extending the Carry Look-ahead Adder

• Four-bit adder on previous chart illustrates
  concept
• To build a practical adder, we need to extend the
  Carry Look-ahead (CLA) circuit
• The carry-out (C4) term requires a 5 input gate
• Hence if we try to build an 8-bit CLA, we will
  need a 9-input gate for C8
• This is similar to the problem we were trying to
  avoid
• Solution
• Consider the 4-bit CLA adder to be a group
• Define Group Generate, Group Propagate, and Group
  Carry terms
• Use CLA circuit again connecting groups

9
Group CLA Equations

• Group Generate
• Group Propagate
• Group Carry
• Defining the Group Variables this way allows us
  to use the extended CLA unit across groups of
  four four-bit CLA adders

GG0 G3 P3 G2 P3 P2
G1 P3 P2 P1 G0
GP0 P3 P2 P1 P0
C4 GC0 GG0 GP0 GC-1
10
Practical CLA Adder
11
Full Adder Module
//fulladder_c.v // //First define the full adder
module // module fulladder_c(a, b, cin, sum,
propagate, generate) input a,b,cin output
sum,propagate, generate assign generate a
b assign propagate a b assign sum
propagate cin endmodule
12
Carry Look-ahead Module
//cla.v //Now define the CLA module // module cla
(G, P, cin, C, GG, GP, cout) input 30 G,
P input cin output 41 C output GG, GP,
cout wire 41 C assign C1 G0 P0
cin assign C2 G1 P1 G0
P1 P0 cin assign C3 G2 P2
G1 P2 P1 G0 P2 P1
P0 cin assign C4 G3 P3
G2 P3 P2 G1 P3 P2
P1 G0P3 P2 P1 P0
cin assign GG G3 P3 G2 P3
P2 G1 P3 P2 P1
G0 assign GP P3 P2 P1
P0 assign cout C4 endmodule
13
Four-bit CLA Adder
//add_4_cla.v //Now build a 4-bit CLA
adder // module add_4_cla (A,B,cin,SUM,GG,GP,cout)
input 30 A, B input cin output 30
SUM output GG,GP,cout wire 30 G, P wire
40 C fulladder_c FA3(A3, B3, C3,
SUM3, P3, G3) fulladder_c FA2(A2, B2,
C2, SUM2, P2, G2) fulladder_c FA1(A1,
B1, C1, SUM1, P1, G1) fulladder_c
FA0(A0, B0, C0, SUM0, P0, G0) cla
CLA (G, P, cin, C, GG, GP, cout) endmodule
14
16-bit CLA Adder
//CLA_16.v //A sixteen bit carry look ahead
adder //Includes a re-worked full adder
module //and a Carry Look Ahead Circuit // module
CLA_16 (A,B,cin, SUM, cout) input 150 A,
B input cin output 150 SUM output
cout wire 30 GG, GP wire 40
GC add_4_cla CLA15_12 (A1512, B1512,
GC3, SUM1512, GG3,GP3,GC4) add_4_cla
CLA11_8 (A118, B118, GC2, SUM118,
GG2,GP2,GC3) add_4_cla CLA7_4 (A74,
B74, GC1, SUM74,GG1,GP1,
GC2) add_4_cla CLA3_0 (A30, B30, cin,
SUM30,GG0,GP0, GC1) cla GCLA0 (GG,PP,
cin, C, GGG, GGP, cout) endmodule
15
16-bit CLA Adder Timing
16
16-bit Adder Behavioral Specification
//add_16_behavioral.v //attempt to specify a
16-bit adder module add_16_behavioral (A, B, cin,
SUM, cout) input 150 A,B input
cin output 150 SUM output cout assign
cout, SUM A B cin endmodule
17
16-bit Adder Behavioral Specification Timing
18
Timing Results

• 16-bit Ripple Carry results in 29 ns add time
• 16-bit CLA results in 22 ns add time
• 16-bit behavioral spec results in 17 ns add
  time
• WHY?