ECE 444

1
ECE 444

• Session 3
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com

2
Operators

• Verilog uses following operator categories
• arithmetic
• Relational
• Equality
• Logical
• Bitwise
• Reduction
• Shift
• Conditional
• Concatenation and replication

3
Table of Operators
4
Table of Operators (cont)
5
Table of Operators (cont)
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Table of Operators (cont)
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Continuous Assignment

• Used to model data flow behavior
• Assigns a value to a net (cannot be used to
  assign a value to a register)
• Example (full adder)

//fulladder.v //Full Adder Module using minterm
equations module fulladder(a,b,cin, sum,
cout) input a, b, cin output sum,
cout assign sum !a !b cin !a b
!cin a !b !cin a b cin assign
cout !a b cin a !b cin a
b !cin a b cin endmodule
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Continuous Assignment (cont)

• Continuous assignment executes whenever an event
  (change of value) occurs for an operand used in
  the right-hand side of the expression
• Target in a continuous assignment statement
• scalar net
• vector net
• constant bit-select of a vector
• constant part-select of a vector
• concatenation of any of the above
• Can appear as part of a net declaration
• Example
• wire Clear
• assign Clear b1
• is equivalent to
• wire Clear b1

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Procedural Constructs (Behavioral Modeling)

• Assignment to registers always statement
• executes repeatedly
• Always Statement Syntax
• always timing_control procedural_statement
• timing_control may be a delay control, or an
  event control
• procedural_statement is one of the following
• procedural_assignment (blocking or non-blocking)
• procedural_continuous_assignment
• conditional_statement
• case_statement
• loop_statement
• wait_statement
• disable_statement
• event_trigger
• sequential_block (begin end)
• parallel_block
• task_enable (user or system)

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always statement

• Examples
• always
• _at_ (negedge Clk)
• begin
• .
• .
• .
• end
• The timing control is on the negative edge of the
  clock
• The procedural code is enclosed between begin and
  end

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Event Control

• Edge-triggered or level-sensitive
• Edge-triggered
• _at_ event procedural_statement
• e.g.
• _at_ (posedge Clock)
• current_state next_state
• _at_ (posedge Clear or negedge Reset)
• Q 0
• Level-sensitive Edge Control
• delay procedural statement until an event becomes
  true
• wait (condition) procedural_statement
• Example
• wait (DataReady)
• Data Bus

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Latch Example

• D latch
• The output, Q, follows the input, D, as long as
  control is enabled
• Verilog Example

D Q C !Q
//D_latch.v //Verilog file to describe a D
latch module D_latch (Q, D, control) output
Q input D, control reg Q always _at_ (control
or D) if (control) Q D endmodule
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Flip-flop Example
Set D Q Clk !Q Rst

• D flip-flop
• Q follows D on positive edge transition of clock
• May have asynchronous set and clear (reset)
  inputs
• Verilog Example

//D_FF.v //D flip-flop example with set and reset
asynchronous inputs module D_FF (Q, D, CLK, SET,
RST) output Q input D, CLK, SET, RST reg
Q always _at_ (posedge CLK or negedge RST or
negedge SET) if (RST) Q 1'b0 else if
(SET) Q 1'b1 else Q
D endmodule
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Basic Design Methodology

• Modern Designs are Complex
• Thousands to millions of gates
• First prototypes must either work or require only
  a few corrections
• Debugging designs much easier at Verilog stage
  than at hardware stage
• Good Design Teams Enforce a Disciplined Approach
• Process to follow
• Rules about design approach
• Constraints
• Modular approaches
• Hierarchical structures

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Design Flow for Small Modules
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Design Specification

• Deals with behavior and interface of each module
  in the design
• Covers multiple levels
• At Module Level, Specification Should Include
• Description of top-level behavior of the module
• Description of all inputs and outputs
• Description of I/O timing and constraints
• Performance requirements and constraints
• May include behavioral prototyping
• Develop software simulation of total design and
  significant modules
• Use your favorite language (C, C, Java, Basic,
  etc.)
• Use specialized languages

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Specification ExampleFour-bit slice, ripple
carry adder module

• Inputs
• Two 4-bit vectors(A30 and B30)
• A 1-bit carry-in (used to concatenate bit slices)
• Outputs
• A 4-bit sum, S30
• A 1-bit carry-out (used to concatenate bit slices
  and to indicate overflow)
• Functional Behavior
• Forms S ABcarry-in
• Generates carry-out as required
• Timing
• Operates asynchronously
• Generates stable Sum and Carry-out within 10
  gate-delays of inputs becoming stable
• Other Considerations
• None (for now)

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Design Structure

• Obtain/Specify Sub-modules Required
• Continue this process until the lowest level
  module is defined or embedded primitives can be
  used
• Determine the control strategy (if any)
• Clearly separate data path from control
• Determine the register transfer level of the
  design
• Module I/O
• Identify, name, and determine the function of
  each module input/output signal
• Registers and register outputs
• Identify each register and name register outputs
• Determine register clocking
• Combinatorial Logic Blocks and their functions
• Identify blocks of combinatorial logic, their
  functions, and name their signals

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Structure ExampleFour-bit slice, ripple carry
adder module

• Sub-module Full-adder
• I/O
• Inputs
• One-bit quantities a, b, and carry-in
• Outputs
• One-bit quantities sum and carry-out
• Functional behavior
• Forms s a b carry-in
• Generates carry-out if necessary
• Timing
• Operates asynchronously
• Generates stable Sum and Carry-out within 10
  gate-delays of inputs becoming stable
• Other Considerations
• None (for now)

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Structure Example (cont)Four-bit slice, ripple
carry adder module

• Determine the control strategy (if any)
• Asynchronous
• Determine the register transfer level of the
  design
• Module I/O
• FA0full adder for bit 0
• Inputs A0, B0, carry-in
• Outputs S0, c0
• FA1 full adder for bit 1
• Inputs A1, B1, carry-in
• Outputs S1, c1
• FA2 full adder for bit 2
• Inputs A2, B2, carry-in
• Outputs S2, c2
• FA3 full adder for bit 3
• Inputs A3, B3, carry-in
• Outputs S1, carry-out
• Registers and register outputs-- None
• Combinatorial Logic Blocks and their functions
  (see above)

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Design Entry

• Create Verilog description for each sub-module
• Create Verilog description for the module by
  connecting the sub-modules and (possibly
  additional logic)

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Design Entry Example Four-bit slice, ripple
carry adder module

• Sub-module full-adder

//fulladder.v module fulladder (a, b, cin, sum,
cout) input a, b, cin output sum,
cout assign cout, sum a b cin
//behavioral assignment endmodule
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Design Entry Example (Cont) Four-bit slice,
ripple carry adder module

• //add_4_rc.v
• //Four-bit ripple carry adder example
• //Uses fulladder.v module
• module add_4_rc(A, B, cin, SUM, cout)
• input 30 A,B
• input cin
• output 30 SUM
• output cout
• wire c0,c1,c2
• fulladder FA3(A3, B3, c2, SUM3, cout)
• fulladder FA2(A2, B2, c1, SUM2, c2)
• fulladder FA1(A1, B1, c0, SUM1, c1)
• fulladder FA0(A0, B0, cin, SUM0, c0)
• endmodule

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Assignment 2

• Goal
• Learn about specifying and structuring modular
  designs
• Continue to review combinatorial design
• Practice Entering designs in Verilog
• Continue to become familiar with Quartus
• Due Monday, 1/21/2004
• Develop the specification, structural description
  and verilog code for a 16- bit, ripple carry
  adder. Evaluate your timing specification by
  examining the output reports of the Quartus
  compiler.
• Test each lower level module completely using the
  simulation feature of Quartus and spot check the
  16-bit adder via the simulation