ECE 444

1
ECE 444

• Session 9
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

2
Counters

• Binary up/down counter
• Inputs
• Inc
• Dec
• Data
• Clock
• load
• Outputs
• Count
• Behavior
• If inc is true, count count 1 on clock edge
• If dec is true, count count 1 on clock edge
• If ld is true, count data on clock edge
• If inc and dec are true, count count
• Load takes priority over count

3
Binary Up/Down Counter
data
load
inc
dec
clock
count
4
Verilog for up/down counter
//up_down_counter.v //parameterized binary
up/down counter module up_down_counter(COUNT,clk,i
nc,dec,load,DATA) parameter width 4 output
width-10 COUNT input width-10
DATA input clk, inc,dec,load reg
width-10COUNT always _at_(posedge clk) if
(load) COUNT lt DATA else if (inc dec)
COUNT lt COUNT else if
(inc) COUNT lt COUNT 1 else if (dec) COUNT
lt COUNT -1 else COUNT lt COUNT endmodule
5
Simulation Results
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More Counter Types

• Ring Counter
• Circular shift register with only one bit set
• BCD (Binary Coded Decimal)
• Counts from 0000 to 1001. Next count after 1001
  is 0000
• Johnson Counter

7
Separating Data Path and Control

• Design Guidelines Suggest Separating Data Path
  and Control
• One Approach
• Use Combinatorial Logic for Data Path Functions
• Use Sequential (State Machine) Logic for Control
• Integrate with top level module
• Connects pieces together

8
A Partial Computer
9
Building Blocks for our Partial Computer

• Memory
• Registers
• Memory Address Register (MA)
• Memory Data Register (MD)
• Instruction Register (IR)
• Register/Counter
• Program Counter (PC)
• Control Unit
• FSM that issues all control signals

10
Memory
module mem ( address, we, outenab, dio) inp
ut 70 address input we input
outenab inout 70 dio lpm_ram_io lpm_ram_io
_component ( .dio (dio), .outenab
(outenab), .address (address), .we
(we)) defparam lpm_ram_io_component.intended_d
evice_family "UNUSED", lpm_ram_io_component.lp
m_width 8, lpm_ram_io_component.lpm_widthad
8, lpm_ram_io_component.lpm_indata
"UNREGISTERED", lpm_ram_io_component.lpm_address
_control "UNREGISTERED", lpm_ram_io_component.
lpm_outdata "UNREGISTERED", lpm_ram_io_compone
nt.lpm_file "mem_test.mif", lpm_ram_io_compone
nt.use_eab "ON", lpm_ram_io_component.lpm_type
"LPM_RAM_DQ" endmodule

• Use the Altera Wizard to Generate Memory Module

11
Register

• Create a Module to be used as a Register
  (multiple instances)

//greg.v //A general register used in the
machine module greg(X, ld, clk,Y) parameter
width8 input width-10 X input ld,
clk output width-10 Y reg width-10
Y always _at_(posedge clk) if (ld) Ywidth-10
lt Xwidth-10 endmodule
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Register/Counter

• Create a Register/Counter Module for the Program
  Counter

//reg_counter.v //A register counter used for the
program counter module reg_counter(X, ld, clk,
inc,Y) parameter width8, increment1 input
width-10 X input ld, clk, inc output
width-10 Y reg width-10 Y always
_at_(posedge clk) if (ld) Ywidth-10 lt
Xwidth-10 else if (inc
!ld) Ywidth-10 lt Ywidth-10
increment endmodule
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Control Unit

• Generate Control Signals and Manage Timing

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Putting it Together

• Now that we have defined all of the building
  blocks, how do we put them together
• This examples integrates many of the items
  discussed earlier
• Refer to the following chart to map the Verilog
  to our problem

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Putting it Together (cont)
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Putting it Together (cont)
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Memory Initialization
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Initial Simulation (Clock Period 100 ns)
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Simulation (Clock Period 20 ns)
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Simulation (Clock Period 10 ns)
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Summary

• Design examples provide fundamental tools needed
  to implement a design.
• Organizing design files can make job easier
• Use Separate Directories e.g.
• SRC - CPU
• - RAM
• - register
• - register-counter
• My top level directory for this effort was SRC
  (contains only folders)
• Separate projects were developed for the Memory
  (RAM), register (g_reg), and the register-counter
  (reg_count)
• The main project is located in the CPU folder and
  is called CPU
• When building the CPU project, add the other
  required files to the project but leave them in
  their respective folders

22
Extending the Example

• The above example provided a partial computer
  control unit
• Instructions were fetched sequentially from
  memory but nothing was done with them.
• Lets continue with this example to illustrate a
  prototype instruction decoder process.
• Let the operation code be contained in the first
  three bits of the instruction register.
• Expand the state table to include an additional
  eight states to correspond to the eight possible
  instructions
• Use the decoder output to generate the next state
  for the state machine

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Extended RTL
     
24
Extended Fetch (Includes Decoder Prototype)
25
Simulation
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Serial Data Transmission

• RS- 232
• Standard Serial Ports for PC
• Interfaces based on devices called UARTs
• Universal Asynchronous Receiver Transmitter
• Asynchronous Communication
• Each character sent asynchronously
• Receiver must detect the beginning and end of
  each character
• Rates are relatively slow (300, 600, 1200, 2400,
  4800, 9600, 14400, 28800, etc.)
• Reference page 378 in text
• Read for next time

27
Signal Definition

• Start Bit
• High for one bit time
• Data Bits
• Transmitted LSB first
• Characters usually transmitted in 7-bit ASCII
  format
• Eighth data bit is a parity bit
• Stop Bit
• Low for at least one bit time
• Rest State
• State of signal between characters
• Low

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PC Comm Port Signal Levels

• Voltage Levels are 12.5 V and 12.5 V
• Rest State is 12.5 V
• Logic 1 is 12.5 V
• Logic 0 is 12.5 V

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UART Receiver Architecture