ECE 444

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ECE 444

• Session 12
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

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Multiplication

• Fixed Point
• Unsigned
• Signed
• Floating Point

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Fixed Point Unsigned Multiplication

• Similar to algorithm used to multiply by hand
• Multiplying two n-bit numbers can result in a
  2n-bit product

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Combinatorial Multiplier
B1 B0 A1 A0
A0B1 A0B0 A1B1
A1B0 _____________________________ S3
S2 S1 S0
NOTE S0 A0B0 S1 A0B1
A1B0 S2 A1B1A0B1
A1B0 S3 A1B1A0B1
A1B0
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Combinatorial Multiplier
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Sequential MultiplierHardware Implementation of
Unsigned Multiply
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Multiply Process

• Clear A and C
• Put multiplicand in M and multiplier in Q
• If q0 is one, add multiplicand to A, then shift
  C,A,Q to right (fill C with a zero from the left)
• Continue process until n steps (four in example)
  have been completed
• n is the number of bits in the multiplier

Multiplicand 1101 Initial Value
C A Q 0
0000 1011 Initial
Value n 4 0 1101
1011 Add M to A 0
0110 1101 Shift Right one
position n 3 1 0011
1101 Add M to A 0 1001
1110 Shift Right one position n 2
0 0100 1111 Shift Right one
position (No Add) n 1 1
0001 1111 Add M to A 0
1000 1111 Shift Right one position (A,Q
contains product) n 0
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Verilog (Note This code is not fully debugged)
//mul_4_u.v //unsigned 4 bit multiplier module
mul_4_u(Min, Qin,Prod,strt, clk) parameter
width 4, count4 input strt, clk input
width-10 Min, Qin output 2width-10
Prod reg width-10 M,A,Q,Cnt reg
2width-10 Prod reg C
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Verilog (cont)
always _at_(posedge clk or posedge strt) if
(strt) begin M Min //note use of
blocking operators A 4'b0000 Q
Qin Cnt 4'b0100 C 0
end else if (Cnt ! 0) case
(Q0) 0 begin
Awidth-10,Qwidth-10C,Awidth-10,Qwid
th-11 C0 Cnt Cnt-1
end 1 begin C,A M
A Awidth-10,Qwidth-10C,Awidth-10
,Qwidth-11 C0 Cnt Cnt-1
end endcase else Prod
Awidth-10,Qwidth-10 endmodule
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Simulation
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Signed Multiplication

• Approach 1
• Use unsigned multiplier
• Sign of answer is XOR of signs of multiplicand
  and multiplier
• Complement negative numbers and multiply as
  unsigned
• Add sign bit at end
• Approach 2
• Extend multiplier to work with twos complement
  numbers directly
• Extend sign of negative numbers to full width
• Multiply as before
• Retain rightmost n bits

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Example
1111 (-1)10 0001 (1)10 1111
0000 0000 0000 00001111
(15)10
11111111 (-1)10 0001 (1)10 11111111 00000
00 000000 00000 11111111 (-1)10
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Using the previous hardware
Multiplicand 1111 Initial Value
C A Q 1
0000 0001 Initial Value
1 1111 0001 Add M to
A 1 1111
1000 Shift Right one position 1
1111 1100 Shift Right one position
1 1111 1110 Shift Right one
position (No Add) 1 1111
1111 Shift Right one position (A,Q contains
product)
Works by shifting in sign bit of multiplicand
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Timing

• This algorithm requires a maximum of n shifts and
  n adds or 2n total operations
• Speed up by parallel multiplier or rework
  algorithm
• Rework Approaches
• Booth
• Shifts over ones
• String of ones in the multiplier from bit u to
  bit v
• Equivalent to 2u1 2v
• booth algorithm recodes the multiplier to this
  form

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Example
010101 (21)10 Multiplicand 001110 (14)10
Multiplier 010010 Booth Recoded
Multiplier 111111010110 (-21x2)10 00010101000
0 (21x16)10 000100100110 (294)10
Shift
Add
Subtract
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Booths Algorithm

• Works for twos complement numbers
• Does not always reduce the number of operations
• Can compensate by encoding multiple bits
• Worst case n shifts and n/2 adds/subtracts or 1.5
  n operations

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Array Multipliers

• Previous methods were serial multiplication
• They trade simple hardware for speed
• Array multipliers trade more hardware for higher
  speed
• Form product for each multiplier bit in rows
• Sum rows in a pipeline fashion

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Array Element
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Building the Array
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AssignmentDue 3/13/2004

• Goal Develop familiarity with hardware
  multipliers and practice implementing them
• Problem
• Extend the unsigned multiplier to handle unsigned
  numbers of eight bits
• Develop the verilog code and simulate
• Extend the eight bit multiplier to handle signed
  numbers
• Develop the verilog code and simulate
• Build an eight-bit multiplier using the LPM-Mult
  function available in Quartus. Compare its
  performance to your designs.