ECE 444

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ECE 444

• Session 6
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

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RTL

• RTL is a register transfer language
• Formal method of identifying what is going on in
  the machine
• We will use AHPL for our RTL
• Easily maps to state machine design
• Implies required data paths
• Can be written at multiple levels of detail to
  structure the design process

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AHPL Basic Notation

• signals or scalar quantities are represented by
  lower case letters (e.g. x, y, z)
• registers (vectors) represented by upper case
  letters (e.g. IR, PC, MA, MD)
• memories (matricies) are represented by bold
  capital letters (e.g M, R)
• data transfers between components are indicated
  by ? (e.g. MA ? PC)
• We can write the following sequence to describe
  the instruction fetch operation.

• MA ? PC transfer contents of PC to MA
• MD ? MMA transfer memory location given by
  MA to MD
• IR ? MD transfer contents of MD to
  instruction register

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AHPL Operand Conventions
 
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Referencing Elements of a Vector or Matrix

• Vectors or Registers
• Indicate dimension and bit numbering by IR310
• implies 32 bits with MSB numbered 31 and LSB
  numbered 0
• Indicate vector elements using the following
• IR310 ( IR31, IR30, , IR1, IR0 )
• Matricies or Memories
• Indicate number of words and number of bits by
  M10000310
• above indicates a memory consisting of 1001
  32-bit words
• Indicate a particular word in memory by M125 or
  MMA
• MA is a vector containing the memory address
• Indicate a particular bit in a memory word by
  MMA31

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AHPL Operators
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AHPL Operators (cont)
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AHPL Operators (cont)
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Instruction Fetch
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Data Control Paths Implied by Instruction Fetch
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Instruction Fetch Control

• Design a state machine to control sequential
  instruction fetch
• The Instruction fetch sequence is defined by the
  following RTL

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Instruction Fetch Control State Diagram
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//fetch_control.v / A simple computer control
unit example. Fetches sequential instructions
and places them in an instruction register. Unit
includes a reset signal which places the process
at the start./ module fetch_control(rst,clk,state
,mald,mdld,irld,pcinc) input rst, clk output
10 state output mald,mdld,irld,pcinc reg
10 state reg mald,mdld,irld,pcinc parameter
S0 2'b00, S1 2'b01, S2 2'b10, S3
2'b11 always _at_ (posedge clk or negedge
rst) if (!rst) begin mald 0 mdld 0 irld
0 pcinc 0 state S0end else case
(state) S0 begin pcinc 0 mald 1 state
S1 end S1 begin mald 0 mdld 1
state S2 end S2 begin mdld0 irld 1
state S3 end S3 begin irld 0 pcinc
1 state S0 end endcase endmodule
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Simulation Results
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Registers

• Prototype Register
• Functions
• Clear
• Load
• Inputs
• Data
• Clear
• Load
• Clock
• Behavior
• All actions take place on clock edge
• If clear is true, register is loaded with zeros
• If Load is true and clear is false, register is
  loaded from the data inputs
• If load and clear are both false, register
  contents are unchanged

R ? (clear load, clear !load, !clear and
load, !clear !load)/(0, 0, Data, R)
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Verilog
//register.v //A prototype register to illustrate
concepts module register(R, DataIn, clk, clear,
load) parameter width 8 output width-10
R input width-10 DataIn input clk, clear,
load reg width-10 R always _at_(posedge
clk) if (clear) R lt 0 else if (load) R
lt DataIn else R lt R endmodule
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Simulation
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Shift Registers

• Prototype Shift Register
• Functions
• Clear
• Load
• Shift left (logical) SC (1,1)
• Shift right (logical) SC (1,0)
• Shift left circular SC (0,1)
• Inputs
• Data
• Clear
• Load
• Clock
• Shift control (SC)
• Behavior
• All actions take place on clock edge
• If clear is true, register is loaded with zeros
• If Load is true and clear is false, register is
  loaded from the data inputs
• If load and clear are both false, register
  contents are shifted according to value of Shift
  control

R ? (clear load, clear !load, !clear and
load, !clear !load)/(0, 0, Data, ((SC3),
(SC 2), (SC1), (SC0))/((R ?R60,0),(R
?0,R71), (R ?R60,R7), R ?R))
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Verilog
//shiftregister.v //A prototype shift register to
illustrate concepts module shiftregister(R,
DataIn, clk, clear, load, SC) parameter width
8 output width-10 R input width-10
DataIn input clk, clear, load input 10
SC reg width-10 R always _at_(posedge
clk) if (clear) R lt 0 else if (load) R lt
DataIn else case (SC) / Shift left
(logical) SC (1,1) Shift right (logical) SC
(1,0) Shift left circular SC
(0,1) / 0 R lt R
1 begin R71 lt R60 R0 lt R7 end
2 begin R60 lt R71 R7 lt 0
end 3 begin R71 lt R60 R0 lt
0 end endcase endmodule
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Simulation
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Prototype Barrel Shifter

• //barrelshifter.v
• //A prototype barrel shift register to illustrate
  concepts
• module barrelshifter(R, DataIn, clk, clear, load,
  SC,AMT)
• parameter width 8
• parameter N 3
• output width-10 R
• input N-10 AMT
• input width-10 DataIn
• input clk, clear, load
• input 10 SC
• reg width-10 R
• reg N-10 k
• always _at_(posedge clk)
• if (clear) R lt 0
• else if (load) R lt DataIn
• else case (SC)
• / Shift left (logical) SC (1,1)
• Shift right (logical) SC (1,0)
• Shift left circular SC (0,1) /

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Prototype Barrel Shifter (Cont)

• 1 //begin R71 lt R60 R0 lt
  R7 end
• case (AMT)
• 0 begin R70 lt R7-00 end
• 1 begin R71 lt R7-10 for
  (k1klt1kk1) R1-k lt R7-k1 end
• 2 begin R72 lt R7-20 for
  (k1klt2kk1) R2-k lt R7-k1 end
• 3 begin R73 lt R7-30 for
  (k1klt3kk1) R3-k lt R7-k1 end
• 4 begin R74 lt R7-40 for
  (k1klt4kk1) R4-k lt R7-k1 end
• 5 begin R75 lt R7-50 for
  (k1klt5kk1) R5-k lt R7-k1 end
• 6 begin R76 lt R7-60 for
  (k1klt6kk1) R6-k lt R7-k1 end
• 7 begin R77 lt R7-70 for
  (k1klt7kk1) R7-k lt R7-k1 end
• endcase
• 2 //begin R60 lt R71 R7
  lt 0 end
• case (AMT)
• 0 begin R70 lt R7-00 end
• 1 begin R7-10 lt R71 for
  (k0klt1kk1) R7-k lt 0 end
• 2 begin R7-20 lt R72 for
  (k0klt2kk1) R7-k lt 0 end
• 3 begin R7-30 lt R73 for
  (k0klt3kk1) R7-k lt 0 end
• 4 begin R7-40 lt R74 for
  (k0klt4kk1) R7-k lt 0 end
• 5 begin R7-50 lt R75 for
  (k0klt5kk1) R7-k lt 0 end

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Prototype Barrel Shifter (Cont)

• 3 //begin R71 lt R60 R0 lt 0 end
• case (AMT)
• 0 begin R70 lt R7-00 end
• 1 begin R71 lt R7-10 for
  (k0klt1kk1) Rk lt 0 end
• 2 begin R72 lt R7-20 for
  (k0klt2kk1) Rk lt 0 end
• 3 begin R73 lt R7-30 for
  (k0klt3kk1) Rk lt 0 end
• 4 begin R74 lt R7-40 for
  (k0klt4kk1) Rk lt 0 end
• 5 begin R75 lt R7-50 for
  (k0klt5kk1) Rk lt 0 end
• 6 begin R76 lt R7-60 for
  (k0klt6kk1) Rk lt 0 end
• 7 begin R77 lt R7-70 for
  (k0klt7kk1) Rk lt 0 end
• endcase
• endcase
• endmodule

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Simulation
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Register Files and Memories

• Array of registers or a memory structure
• Verilog supports declaration of the type
• reg msblsb memoryupper_address lower
  address
• A register file of 16 eight bit words
• reg70 reg_file150
• Can be used to create memory structures on the
  chip
• WARNING Memories created with this technique
  use considerable resources. If you need a
  memory, use one of the Altera megafunction
  modules.

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Example

• Three port register file
• One write port
• Two read ports
• Each port consists of an address vector and a
  Data vector
• The write port also has a write enable
• 16 registers of 8 bits each
• Read Ports always follow the read address
• Write port writes data at the positive clock edge
  when write enable is true

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Verilog
//three_port_mem module three_port_mem (A, B,
AADDR, BADDR, XADDR, X, we, clk) output 70
A, B input 70 X input 30 AADDR, BADDR,
XADDR input we, clk reg 70 A, B reg
70 reg_file150 always _at_( posedge clk)
begin if (we) reg_fileXADDR X A
reg_fileAADDR B reg_fileBADDR
end endmodule
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Wizard for Memory
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Wizard for Memory (Cont)
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Wizard for Memory (Cont)
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Wizard for Memory (Cont)
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Memory Initialization File

• Create Memory Initialization File (MIF)
• File.New.Other.MIF

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Assignment 4 Due 20 September 2004

• Goal
• Review Sequential Circuit Design
• Practice Verilog constructs for sequential
  circuit design

• Design a four-bit shift register and control
  unit. The shift register will shift right
  logical, shift left logical, and shift left
  circular depending on the value of the control
  input. An additional input required is the
  number of bits to shift. All shifts are
  sequential and shift one position per clock.
  Develop a state diagram, a state table, and write
  an RTL description of the register control unit.
  Write the Verilog HDL and simulate the register.
• Repeat problem 1 for a four-bit barrel shifter
  (shifts in parallel). The control inputs are
  srl, sll, and shc along with the number of bits
  to shift. The complete shift should consume one
  clock period.