Compiler Research at the Indian Institute of Science Bangalore, India - PowerPoint PPT Presentation

1 / 10
About This Presentation
Title:

Compiler Research at the Indian Institute of Science Bangalore, India

Description:

Machine code generation with top-down tree pattern matching ... Hooks into the OS. JIT Compilation. An efficient JIT compiler for .NET CLI on ROTOR ... – PowerPoint PPT presentation

Number of Views:68
Avg rating:3.0/5.0
Slides: 11
Provided by: Srik5
Category:

less

Transcript and Presenter's Notes

Title: Compiler Research at the Indian Institute of Science Bangalore, India


1
Compiler Research at the Indian Institute of
ScienceBangalore, India
  • Y.N. Srikant
  • Professor and Chairman
  • Department of Computer Science and Automation
  • Indian Institute of Science
  • srikant_at_csa.iisc.ernet.in

2
Past Research
  • Automatic generation of incremental parsers and
    semantic analyzers
  • Optimizer generator
  • Machine code generation with top-down tree
    pattern matching
  • New algorithm for partial redundancy elimination
  • Automatic parallelization for distributed memory
    machines
  • Automatic data partitioning based on genetic
    algorithms (for DMMs)

3
Current Research Areas
  • Code Generator Generators
  • Instruction Scheduling
  • Power-aware compilation
  • Just-In-Time compilation

4
Code Generator Generators
  • Emphasis on generating efficient code generators
    from machine descriptions
  • Uses new tree pattern matching alogorithm based
    on LR-parsing (in-house)
  • Integrated into TRIMARAN and is based on LCODE
    intermediate code
  • Tried on DSP (Texas Instr.) and Itanium
  • Faculty member Priti Shankar

5
Instruction Scheduling
  • Faculty members
  • R. Govindarajan, Priti Shankar and Y.N. Srikant
  • New approaches for VLIW and Superscalar
    architectures
  • Integer linear programming
  • Co-scheduling hardware and software pipelines

6
Instruction Scheduling (contd.)
  • Instruction scheduling for clustered DSP
    architectures
  • Integrated scheduling combining clustering and
    scheduling
  • Graph matching based scheduling
  • Integrated into SUIF
  • Experiments with TI 32064X

7
Power Aware Compilation
  • Transition-aware scheduling
  • Reduces the number of transitions from active to
    low-power and vice-versa
  • Saves energy
  • With XScale, XTREM, and gcc
  • Experiments with heterogeneous interconnects in
    clustered VLIW architectures
  • Two interconnects, one with high speed and high
    power requirement, another with lower speed and
    lower power requirement
  • Experiments with TRIMARAN (suitably modified)

8
Power Aware Compilation (contd.)
  • Experiments with Object cache
  • Separate cache for objects
  • Combination saves energy and is as fast as a
    general purpose cache
  • Use of static analysis and profiling to classify
    objects as long living and short living
  • A Framework for writing power aware applications
    with ECOS
  • Hooks into the OS
  • ??

9
JIT Compilation
  • An efficient JIT compiler for .NET CLI on ROTOR
  • Profile-guided optimizations
  • Cluster and Collect concurrent garbage
    collector
  • Detects long-living clusters of objects by
    profiling and static analysis
  • Allocates them in a separate mature object space
  • Stack allocation for scoped objects
  • Architectural innovations to speedup profile
    collection
  • Low profiling speed is the bottleneck with
    profile-guided optimizations
  • Most common types of profiling can be carried out

10
Thank You
  • Questions?
Write a Comment
User Comments (0)
About PowerShow.com