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Dr. Shamik Sural

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A Synergistic Relationship between IIT Kharagpur and National Dr. Shamik Sural Assistant Prof., School of Information Technology & Co-Consultant TRET Project ... – PowerPoint PPT presentation

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Title: Dr. Shamik Sural


1
A Synergistic Relationship between IIT Kharagpur
and National
  • Dr. Shamik Sural
  • Assistant Prof., School of Information Technology
  • Co-Consultant TRET Project - National
    Semiconductors
  • INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR, INDIA.

2
Contents
  • Introduction to IIT Kharagpur
  • IIT Kharagpur National Relationship
  • TRET Project
  • Object Oriented Template Design
  • Resistance Extraction Tool for Rds-on
    Optimization
  • New Project on Optimization Tool

3
Indian Institute of Technology Kharagpur
  • IIT Kharagpur
  • Largest, Oldest of 7 IITs
  • Best chip design centre in India
  • with world class activity
  • Nodal Center for MEMS
  • EECS Laboratories/ Centres
  • Advanced VLSI Design Lab
  • Microelectronics Centre
  • MEMS Design Centre
  • Material Science Centre
  • Media Lab Asia
  • Centre for Educational
  • Technology
  • DSP Lab (TI Motorola)
  • Microsoft Laboratory
  • EECS Departments Related Schools
  • Departments
  • Electrical Engineering
  • Electronics Electrical Communication Engg
  • Computer Sc Engineering
  • Schools
  • GSS School of Telecommunications
  • School of Information Technology
  • School of Medical Science Technology

4
RD on VLSI Design and CAD in India
  • Projects
  • Equipment
  • Research Fellowships
  • Research Grant
  • Infrustructural
  • support

Govt. of India
Industry
R D Centers of Excellence
I.I.T. Kharagpur
  • Exchange Programme
  • Joint collaborative
  • Research Projects
  • Manpower Training
  • Tools Management
  • Fab Test Support

Foreign Universities
UG Education
5
Advanced VLSI Design Lab History
  • IIT Kharagpur sets up the Advanced VLSI Design
    Lab in May 2000 with an objective to achieve
    excellence in research in VLSI Design and train
    students to tape out actual chips
  • IIT Foundation (Group of Successful Alumni based
    in the Silicon Valley) donates about 1 million
    in 3 years to set up a platform. IIT Kharagpur
    provides prime laboratory space, changes rules
    and encourages this multi-disciplinary activity
    to the fullest
  • National Semiconductor offers Cost-free FAB under
    the Planets Program

6
Advanced VLSI Design Lab The finest Chip Design
Lab in India
  • Partners
  • IIT Foundation
  • National Semiconductor
  • Sun Microsystems
  • Cadence
  • Synopsys
  • Agilent
  • Some Chips Designed
  • Rijndael Encryption
  • Baseband Processor
  • for 3G WCDMA
  • 2.45 GHz PLL VCO
  • Voltage Regulators
  • Galois Field Processor
  • 6-bit, 100 MHz ADC
  • 900 MHz QPSK Modem
  • Pipelined DLX Processor
  • Used by 100 students and 20 faculty of IIT
  • More than 20 publications in 2002-03
  • Wins Design Contest in VLSI 03 Conference
  • Collaboration with GaTech, U Washington, UMich
  • Training by International Scholars
  • Intensive in-house courses
  • Designed more than 25 chips in 0.25, 0.18 and
  • BiCMOS
  • Plans to make it a National Centre of Excellence

7
Facilities Available
  • Computing Resources
  • Sun Enterprise 450 Server
  • 10 Sun Ultra-60 Dual Processor Workstations
  • 50 SunRay Thin Clients
  • Windows Workstations
  • Software
  • Cadence Verilog XL, Silicon Ensemble, Analog
    Artist, Ambit Tools
  • Synopsys Front and Back-end University Package
    including Design Compiler, Prime Time, Vera, etc
  • Mentor Graphics Tools
  • MAGMA Tools
  • Design Libraries
  • National Semiconductor 0.25u, 0.18u CMOS, BiCMOS
  • SCL, Chandigarh
  • 1.2u, MEMS Fabrication
  • Test Equipment
  • Semiconductor Parameter Analyzer
  • Network Analyzer
  • Logic Analysis System
  • Noise Figure Test Set
  • Digital Storage CRO
  • Multipurpose Test Equipment and accessories

8
Achievements
  • Recognition Industry personnel from National,
    TI, AD, SCL recognize this to be the best
    University-level VLSI Design Laboratory in India.
    More than 25 chips have been taped out.
  • Funded Projects The Laboratory has been able to
    attract funded industry projects from National,
    Intel, Sun, Synopsys, etc. valued at about US1
    Million during the last three years
  • Research Team About 20 faculty members of EECS
    disciplines are involved in this Laboratory. More
    than 40 IIT graduates with excellent academic
    records and toppers from other Universities are
    working in the lab on a full-time basis.
  • Training Our Students and faculty have been
    provided with training by Georgia Tech, Univ.
    Washington, Univ. Michigan under Exchange Programs

9
IIT-National Relationship
  • Funded Projects
  • CAD Tools Enhancement (Mohan/James Lin)
  • Tools Development for CR-16 (Joe Montalbo)
  • DC-DC Converters (Ed Lam, Barry Culpepper)
  • Rake Receiver WLAN (Ahmad Bahai)
  • Development of Parameterized Templates (Reda
    Razouk, Peter Hopper)
  • Behavioral Modeling of OP AMPs (Arie Van Rhijn)
  • High Speed Switched Regulators (Ravi Amabatipudi)
  • Low Power RF Design (Krishnamurthy)
  • IIT graduates hired at National
  • About 6 in National, USA
  • About 6 at National, Bangalore

10
IIT-National Relationship
  • IIT is prepared to take up long-term manpower
    training program for National
  • PhD Students will be hired by IIT from
    National-funded Projects for three years and will
    be absorbed by National on completion
  • Newly recruited National Employees can be deputed
    to work on National projects at IIT and pursue
    higher Degrees
  • IIT is capable and committed to serve as a
    research center for National in Analog, Power,
    Mixed Signal Design, Testing and CAD

11
Templates based Parameterized Layout
Tool for Resistance Extraction
12
Highlights of the TRET Project
  • Object Oriented Template Design
  • Resistance extraction tool for Rds-on
    optimization
  • New Project on Optimization Tool

13
Object Oriented Template Design
14
Parameterized Layout The Big Picture
15
Issues in Template Design
  • Hierarchical Approach
  • Device Template
  • Placement Template
  • Routing Template
  • Pad Template
  • General Requirements
  • Design Rule Compliance, i.e., Correct-by-construct
    ion layouts
  • Templates to work on a generic set of design
    rules which cover a good number of processes
  • Template code to be very modular to allow for
    future changes and new recommendations
  • Object Oriented approach suits best for writing
    systematically modular code in a hierarchically
    decomposed system

16
Object Oriented Methodology
  • Templates are hierarchical composites of objects
  • Classes are defined containing private variables
    and methods to access them
  • The key concepts of abstraction, encapsulation,
    inheritance, polymorphism have been incorporated
  • Initiative on building an array of essential
    intermediate classes, which are built using the
    SI primitives and can be used to construct
    complex device templates

17
Example Class Diagrams
18
Example Class Diagram
19
Routing Templates
  • Classes of Routing problems
  • DC routing
  • Routing for Matching structures
  • Kelvin Routing for Resistance measurement
  • Routing of RF structures
  • Algorithms used
  • Line Probe Routing
  • Maze Routing
  • Special techniques
  • Connection graph based method for economic
    variable width routing
  • Presented at VLSI Design and Test Workshop 2004,
    Mysore, India in August

20
Maintainable code development
  • To improve the readability of codes developed
  • Brief overview of the algorithm provided at the
    starting of the code
  • All functions accompanied with description
  • Standard Java nomenclature followed
  • Self-explanatory variable names
  • Detailed modularization of code

21
Example Quad using DC routing
22
Future Directions
  • Extension of the DC routing Class diagram to
    include other classes of routing problems
  • Go through routing of matching structures, Kelvin
    routing and RF routing, in that order
  • Develop a class diagram for Placement algorithms
    complementary to and in parallel with the routing
    class diagram --- This will enable future plans
    of routing optimization with both placement and
    routing in the loop
  • Stone Pillar to make Silicon Insight a complete
    platform for object oriented template library
    development --- IIT to subsequently build device,
    placement and routing libraries

23
Resistance extraction tool (To be
used for Rds-on optimization of large power
arrays)
24
Overview
  • Required features
  • Handling arbitrary non-linear geometries
  • More accurate than Star-RC
  • Tool to have a matrix solver inside no need to
    go to SPICE
  • Should be able to give current densities at
    various points in the layout for thermal analysis
  • Less complex than full-scale electromagnetic
    simulators
  • Compatibility with Silicon Insight
  • To be portable to run with an optimizer for Rdson
    optimization of power arrays

25
General Picture
26
System Overview
27
Algorithm Overview
  • Atomic Steps in the flow
  • Merge polygons in Silicon Insight
  • Flatten layout geometry information and decompose
    into domains
  • Finite element mesh each domain and formulate
    potential difference equations for the mesh nodes
  • Form a co-efficient matrix and solve for the
    admittance matrix of the domain
  • Combine the admittance matrix of all domains and
    collapse this matrix for a given set of external
    electrodes

28
Generic Tool for Optimization
29
General Requirements
  • Two general classes of problems
  • Device and Process simulator calibration
  • Optimal design of processes, devices and circuits
  • Ability to handle various different device models
    describing different regions of operation and the
    hard non-linearity cropping in as a result of
    this
  • Tool to provide a visual display showing the
    progress of the optimization process
  • Algorithms for CPU cost minimization as these
    optimization processes would be generally very
    expensive

30
Block Level Diagram
31
Plan
  • Investigate the following
  • Utility of standard optimization algorithms (
    both classic and stochastic ) for the different
    classes of problems
  • Formulation of appropriate observable state
    variables for these problems
  • Online monitoring based principles to build
    intelligence in the tool for learning and making
    stochastic decisions during the run-time of the
    optimization routine
  • Implement the optimization engine code and the
    GUI in Java

32
Conclusions and Summary of the TRET Project
  • Completely Object-oriented approach to
    parameterized layout development with
    capability-building towards a drag-and-drop kind
    of environment
  • Managing the complexity of the resistance
    extraction tool for Rds-on optimization of
    arbitrarily non-linear Power arrays
  • Optimization framework development for a wide
    range of TCAD applications

33
Thank You
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