Measurements of the first ON Semiconductor production wafers at Udine

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Measurements of the first ON Semiconductor
production wafers at Udine

• Prepared by Diego Cauz
• on behalf of the group of Udine
• April 2004
• Udine

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Measurement speed-up

• Doctor Sergey Gorokhov is back in Udine since
  April 14th.
• He will stay for 3 months

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ON-Semic wafers in Udine

• We have received 11 ON Semiconductor wafers in
  April
• 2 partially measured for quick shipping to AMS

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Visual inspection (VIS)(1/3)
Mask Align (H-V) Wafer
n-side L n-side R p-side L p-side
R ID marking
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Visual inspection (VIS)(2/3)
Mask Align (H-V) Wafer
n-side L n-side R p-side L p-side
R ID marking
Bad passivation vernier in the 4th vernier
pair on all 4 monitors, both H and V, all
wafers. See next slide
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Many defects, probably scratches on the tiles of
9688-07
Tile 1 8 scr.s -93 pix Tile 2 4 scr.s -20
pix Tile 3 9 scr.s -122 pix
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Wetting residue
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Visual inspection (VIS)(3/3)
AMS communication
bad on limited areas
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9688-10
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1203-11
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Thickness measurement (THI)
220 mm lt th lt 260 mm
Dth lt 10 mm
Wafer th1 th2 D (mm)
Wafer th1 th2 D (mm)
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I-V on diode w/ guard ring (IVD)
Iop I(Vop)
Vbd max V(I lt 25 nA)
Wafer Vbd (V) Iop (nA)
Wafer Vbd (V) Iop (nA)
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C-V on diode w/ guard ring (CVD) (1/2)
Measurement very noisy. One cable found
defective. Large incertitude on Vdep.
Vdep Cdep Vop r
Wafer (V) (pF) (V) (W
cm)
Vop max(150 V, Vdep 50 V)
Vdep V(kink in C-V curve)
Cdep C(Vdep)
30 lt Vdep (V) lt 120 2000 lt r (W cm) lt 5000
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C-V on diode w/ guard ring (CVD) (2/2)
Vdep Cdep Vop r
Wafer (V) (pF) (V) (W
cm)
See next slide
Vop max(150 V, Vdep 50 V)
Vdep V(kink in C-V curve)
Cdep C(Vdep)
30 lt Vdep (V) lt 120 2000 lt r (W cm) lt 5000
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I-V on tiles (1/2)
Wafer Vop (V) Vbd (V)
S good tiles
Vbd gt Vop S I(Vop) / I(Vop-50) lt 2
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I-V on tiles (2/2)
Wafer Vop (V) Vbd (V)
S good tiles
Bad I-t
Vbd gt Vop S I(Vop) / I(Vop-50) lt 2
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I-V on SCs
Only half of the SCs are being measured
Wafer good/total
Wafer good/total
Vbd gt Vop S I(Vop) / I(Vop-50) lt 2
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I-V on MCs
Only half of the MCs are being measured
Wafer good/total
Wafer good/total
Vbd gt Vop S I(Vop) / I(Vop-50) lt 2
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I-t on good tiles (ITS)
S Iend / Istart lt 1.3
Wafer-tile S
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I-V on MOS (BOX)
delay 4 s
Wafer Vbd (V)
Wafer Vbd (V)
Vbd max V(I lt 100 pA) gt 50 V
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C-V on MOS (COX)
Wafer Cox (pF) Cmin (pF) CFB (pF) VFB (V)
Cox Cmax VFB V(C nearest to CFB)
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I-V on gate-controlled diode (IVG)
Wafer Itop (pA) Ibot (pA) Iox(pA)
Itop I(VFB 3 V) Ibot I(VFB 3 V)
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COX, IVG discrepancy
VFB is around 16 V
VFB is around 4 V
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I-Vg on MOSFET (MFE)
Wafer Vth (V) p-dose (x 1012 cm-2)
Vth is usually good, but I beyond threshold is
very low. See next slide.
2.2 lt p (1012 cm-2) lt 3.5
Vth max V(I lt 100 nA) gt 0
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Vpix-V on punch-thru structure (PUT)
Vpt gt3 V
Wafer Vpt (V)
Wafer Vpt (V)
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Conclusions

• 11 wafers are being measured
• Missing measurements VIS, PLA
• Some measurements need to be done again
• Wafer quality
• bad passivation in the mask alignment monitor for
  all 4th vernier pair, wafers 9688-07, 1203-34
• Many scratches on the tiles of 9688-07
• Bad bump pads for 9688-10 (and 9688-07)
• wafer 1203-34 does not pass MFE test
• wafer 1203-34, 9688-10 have only one good tile
• wafer 1203-27 has no good tile
• Almost all wafers do not pass PUT test

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Conclusions
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Project Progress Tracking
Laboratory tiles meas/total percent

• Dortmund 145/250 58
• New Mexico 0/250 0
• Prague 250/250 100
• Udine 212/250 84
• This tool is not trustable.

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Tile pool

• In reality the 4 labs have received a total of
  1121 tiles, 1060 of which have been accepted
• Dortmund 250
• NM 265
• Prague 250
• Udine 212
• The missing tiles are to be finished measuring by
  Udine (14 wafers) and Dortmund.