Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams

1
Automatic Test Pattern Generation for Functional
RTL Circuits Using Assignment Decision Diagrams

• INDRADEEP GHOSH MASAHIRO FUJITA

Fujitsu Labs. Of America Sunnyvale, CA
2
Outline

• Problem Specification
• assumptions
• Motivation
• Data Structures
• Algorithm
• Experimental Results
• Conclusions and Future directions

3
Problem Specification

• Given
• an HDL description for a circuit at functional
  RTL
• a test set library of different arithmetic
  operations and macros used in the design
• Automatically generate a set of test patterns for
  the circuit which
• provides high stuck-at fault coverage on the
  synthesized gate level circuit (any
  implementation)
• excite each line of code in the circuit and
  propagate to an observable point
• Support hierarchical designs

4
Current Assumptions

• Single clock design in VHDL/Verilog
• No asynchronous behavior supported
• Exception set/reset of flip-flops
• All FSM kind of descriptions (state variables)
  should have
• a reset state and signal or
• some input signal that takes FSM to specific
  state
• Every black box or IP has
• its own stuck-at test set
• a justification and propagation path for each
  output/input to get test data across it

5
Motivation

• Good RTL synthesis tools leading to widespread
  use of functional RTL designs
• ATPG algorithms still perform at logic level
  where sequential ATPG is quite hard
• Because of less number of primitives at RTL ATPG
  should be able to achieve
• faster test generation time
• better fault coverage
• The patterns can be used for RTL-RTL validation
  RTL-gate level validation through simulation

6
Data Structure

• Represent RTL netlist as an Assignment Decision
  Diagram (ADD)
• Previously proposed for high-level synthesis by
  Chaiyakul et.al. (DAC 93)

Assignment Value
Assignment Condition
Assignment Target

• Advantages
• Represents a structural view suitable for
  stuck-at
• testing

7
Testing Technique

• Convert HDL file into a series of ADDs
• each process converted to an ADD
• seq/combinational process for FSMs combined to
  single ADD
• ADDs connected together by read and write nodes
• Infer RTL structural components from ADDs
• Each inferred component is fed its logic-level
  stuck-at test
• 2-to-1 mux 4 vectors
• register / latch 4 / 2 vectors
• logic module well known test set
• memories checker board test
• arithmetic module precomputed test
• an universal test set preferable
• random logic / test set unavailable
• excite HDL code and observe effect at system
  primary output

8
Justification/Propagation on ADDs

f
e
m
Stuck-at Test s b c 0 xxxx
1111 0 1111 0000 1 1111 xxxx 1
0000 1111
g
1
4
s
a
ADD
b
4
RTL
b
s
c
1
c
c
b
4
4

1
if (s 1) a b else a c
0
s
4
not
a
Structure
a
VHDL
Objective - 0 at s All ones at c Observe a -gt
. . . . -gt 1 at input m 0 at e observe g
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Nine Valued Algebra

• Cg ability to control an n-bit bus to any of
  2n value
• C0 ability to control a variable to the 0
  value
• C1 ability to control a variable to the 1
  value
• Ca1 ability to control a variable to the all
  ones vector
• CA1 of 1 bit variable is C1
• Cq ability to control a variable to any
  constant
• Cs ability to control a state variable to a
  particular ...state value
• Cz ability to control to high-impedance state
• O ability to observe an any fault on multi-bit
  ...variable or an 1/0fault on a
  single-bit variable
• O ability to observe a 0/1 fault only for a
  single-bit variable

10
Justification/Propagation Record

• A six valued set
• the ATPG objective, variable name, upper and
  lower bit index of the variable, time frame
  value, and a state value (only in case of Cs)
• Cg(a70, 0, -) a70 should be generally
  controllable in time frame 0.
• Cs(Curr, 3, S0) Curr needs to be S0 in time
  frame 3.
• An objective is justified or propagated through
  RTL constructs.
• c a b Cg(c) -gt (Cg(a) and Cq(b)) or (Cq(a)
  and Cg(b))
• Only few RTL constants are represented as they
  are sufficient to transfer test data across all
  HDL operations

11
Transformation Rules

• For arithmetic/logic modules construct look up
  tables using behavior
• , CG(output) -gt CG(leftin) and CQ(right in) or
  vice versa
• , O(input) -gt O(output) and C1(other input)
  etc
• If there is an edge testing at a control port of
  any ADD node while going across it
• Decrease time frame during justification
• Increase time frame during propagation
• States are transformed until a reset state is
  reached
• CS objective on state variable converted to C0/C1
  of a signal or variable
• Maintain search frontier
• Drop objectives already satisfied
• Backtrack if conflict

12
Path Tracing Example
a, b, c, d std_logic_vector(7 downto 0) r
std_logic_vector
Architecture RTL of new is begin a b c
if (clkevent and clk 1) if (r 1)
d a else e a end
if end if end RTL
Testing Addition Operation
Cg(b70), 0, - Cg(c70), 0, - O(a70),
0, -
Cg(b70), 0, - Cg(c70), 0, - C0(r00), 0,
- O(e70), 1, -
Cg(b70), 0, - Cg(c70), 0, - C1(r00), 0,
- O(d70), 1, -

• Final paths to PIs and POs constitute a test
  environment

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Testing Arithmetic/Logic Operations

• First Arithmetic operations are tested
• apply Cg at all inputs and O at all outputs and
  justify and propagate
• search ends at PI/POs and the series of paths
  across many time frames constitute a test
  environment
• precomputed test sets used with test environment
  to get system level test set
• test set is concatenation of most parallel and
  most serial implementation of operation
• universal test set will be better
• Logic arrays are tested next
• stringent Cg requirement is not used as all test
  sets fall within supported constants

C0(b70, 0)
C0(a70, 0)
C1
C0
8
8
C1
C0
OR
8
O(c70, 0)
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Testing Storage Elements Interconnect
event
a
b
load
1
Clock
v4
v2
v3
v1


and
s1
and
s2
s3
not
s4
and
b
g

• Test of form Ca1(b), O(b)
• and C0(b), O(b)
• Also Ca1(a), C0(b) O(b)
• tests load line

• Tests Ca1(vi), C1(si),O(g)
• and C0(v1), C1(si), O(b)
• Second test is not perfect
• fault simulation catches
• some faults

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Handling Bus Splits/Joins

• Special transformation rules for bus splitting /
  joining
• Split -
• CG -gt CG and CG
• CA1 -gt CA1 and CA1 (C1 if single bit)
• CQ -gt CQ and CQ
• C0 -gt C0 and C0
• C1 -gt C1 of LSB bus segment and C0 to other
  segments
• O -gt O and O
• Join -
• CG and CG -gt CG
• C1 and C1 -gt CA1
• CA1 and C0 -gt CG
• C0 and C1 -gt C1 etc
• O and O -gt O

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Handling Black Boxes and IPs

• A module level stuck-at test set is assumed to be
  provided with every black box and IP
• An algebraic transformation for each input for
  propagation across module assumed provided
• An algebraic transformation for each output for
  justification across module assumed provided

10101 01011 10100
a
O(a, 0) -gt O(b, 3)
c
b
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Value Analysis

• Plug in test set from a test set library into
  test environment to get system level test set
• Concatenate all system level test sets

-13
Cg(n40), 0)
(5, 15) (3, 10)
Test Set
(6 cycle test set)
C0(p40), 0)
Cg(m40), 0)
0
2
Cg(a40), 3)
Cg(b40), 3)
C1(d40), 2)
Cg(e40), 2)
a
5
b
15
d
e
1
-4
RTL Circuit
-
c
a
5
O(c40), 4)
Cg(a40), 3)
O(x40), 5)
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Heuristics for Better Performance

• Partial justification and propagation
• generate partial test environment test set
  accordingly
• Appending fixed number of random vectors to
  justification sequence for propagation
• Identification and handling of counters
• Cg(a, 0) -gt Cg (a, -2), -gt Cg (a, -4)
• Reset counter and run for fixed number of cycles
• Dynamic bus expansion
• Tagging read, write and ADN nodes
• some kind of primitive fault simulation

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Algorithm Summary

• Path tracing
• Place symbolic objective records on variables at
  leaf nodes
• Justify/propagate objectives to component
  boundary using functional information
• Use top level interconnection to further justify
  and propagate objectives across hierarchy until
  system PI/PO is reached
• Algorithm similar to logic level ATPG but at RTL,
  requires backtracking
• Degenerates to an inefficient D-Algorithm if
  given logic netlist
• Final set of paths across many cycles constitute
  a test environment
• Value analysis
• Plug vectors from test set library into test
  environment
• Requires a series of arithmetic/logical
  operations on module level test vector set
• Concatenate all system level test sets

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Experimental Results (1)
RTL-ATPG
HITEC
RTL
Logic
pattern
coverage
time
coverage
time
pattern
Circuit
(sec)
()
(sec)
(cycles)
()
(cycles)
lines
gates
Paulin
130
39558
97.92
147002
752
99.72
138
4124
Tseng
121
22650
98.43
52139
366
99.68
216
3429
Dct
336
13869
90.01
74805
1696
96.50
739
3965
GCD
113
1467
49.16
43964
258
94.31
498
4568
Barcode
156
714
63.41
9799
759
88.78
876
4080
X25
122
2250
36.31
93592
151
85.35
1046
3561
Am2910
543
2109
73.86
18723
1317
95.32
2765
3952
GPIO
1002
1720
99.41
57
1396
93.56
5543
690
ALM
3504
8265
22.53
58600
589
36.52
85654
1430
EXE
8075
12327
21.32
27300
992
40.83
585700
5689
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Experimental Results (2)
paulin
1000
x25
tseng
100
dct
gcd
barcode
Time advantage ( HITEC / ours )
10
am2910
1
alm
10
100
1000
0.1
exe
0.01
gpio
Expand ratio ( gates / lines )
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Conclusions

• Presented an algorithm for RTL ATPG targeting
  stuck-at tests at logic level
• Algorithm gracefully degrades to logic level
  sequential ATPG if given logic like RTL circuit
• Up to 1000 times reduction in test generation
  time obtained on certain circuits
• Fault coverage is not compromised
• Performance degenerates as RTL description is
  more and more logic type

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Future Work

• Map effective logic level heuristics into
  algorithm to make it better than logic ATPG for
  any circuit
• e.g. SCOAP assisted search
• Target up to 100,000 line circuits
• Test vector compaction through RTL fault
  simulation
• Handling multiple clock lines
• Investigating the effectiveness of test set for
  Validation using RTL coverage analysis tools

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Thank You