VHDL FPGA Microprocessor Design 525'442 Doug Wenstrand Joseph Haber

1
VHDL / FPGA Microprocessor Design525.442Doug
WenstrandJoseph Haber
2
Class Goals

• Learn VHSIC Hardware Description Language
• Synthesis of Digital Hardware
• Modeling of Complex Digital Systems
• Testbench Developmemt
• Learn about FPGA design concepts and practices
  and how VHDL can be applied
• Learn about fundamental concepts in
  microprocessor design.
• Use VHDL and FPGA design knowledge to put this
  into practice
• MODIFIED this semester hybrid software/hardware
  systems on chip using commercial microprocessor
  IP cores.

3
Grading Criteria
Laboratory Assignments / Homework (50) Each
week an assignment will be given. Typically this
will give design requirements, and the student
will construct a design in VHDL, and implement it
on the trainer for demonstration. Unless
otherwise specified, each assignment will count
equally towards the cumulative 50 of the class
grade. Unless otherwise specified, assignments
will be due one week from the assigned date by
class-time. No Late Homework is accepted without
prior approval, since solutions will typically be
handed out or discussed. Mid-Term Exam
(25) Material for the midterm may include all
topics in the assigned reading, discussed in
class, or covered in the laboratory assignments.
More details will be given before the exam.
Material covering precise VHDL syntax will be
distributed as part of the exam however,
knowledge of VHDL concepts, and behaviour are
required. Exams will be closed book
4
Grading (cont)
Final Project (25) Though graded differently,
the final project will be very much like the
laboratory assignments different mostly in the
quantity of work. The final project will be to
design in VHDL, simulate in Modelsim, and test a
project based on a microprocessor core
implemented on the FPGA trainer board. The
project will build on the lab assignments done
throughout the semester, so completing them
correctly (and correcting them as required) will
ease the development of the final project.
5
Misc.
Laboratory Assignments are to be completed
independently Helping each other with tools
related problems, class material, or general VHDL
knowledge is, of course, allowed and encouraged
copying of projects from other students or from
the Web is neither. A notable exception is the
first project, for which some of the code comes
directly from the tutorial provided to
you. Projects / Homeworks are to be well
documented and appropriately designed Simply
getting the design to meet requirements for
demonstration is not grounds for 100. The design
should be done in a well organized,
understandable way, with appropriate comments. In
addition, the design should make effective use of
the resources on the chip by implementing pieces
in an appropriate manner. The combination of all
these factors determines the project grade.
Lecture will not always last the entire class
period. The rest of the meeting time will be in
the laboratory, where the instructors will be
present to answer questions as needed.
Demonstration of assignments that are due is also
done during this time period.
6
Homework

• Lab Assignments will typically have some or all
  of these things due
• Design description (similar to the package one
  might deliver before a design review) Actual
  sentences and even paragraphs explaining the
  design
• Archived Project Directory (lab1_lastname.jhu)
• Zip file renamed with jhu extension to pass
  filters
• Code readable and commented
• A .bit file, which when loaded to the
  demonstrator board will produce the final design.
  This is to be submitted electronically by email,
  or by floppy if required.
• Project should build to make above bit file.

7
Class Materials
Book The Designers Guide to VHDL. Peter
Ashenden Additional Materials A development kit
with board, cables, and CD-ROMs will be provided
by the instructor that will contain the FPGA
development tools, and documentation. Course
Website apl.jhu.edu/wenstds1 Contains class
notes and materials that develop as the class
progresses. Class Email Forum vhdlupclass_at_yahoo
groups.com by invitation only if you want an
email address invited that you didnt write on
the class info form, send it to the instructors _at_
work and we will invite you.
8
Schedule
Jan.24 Introduction / VHDL Basics / Simple
Combinatorial Logic / Structural VHDL Jan 31
Sequential logic / processes / RTL design /
Simulator Operation Feb 7 Testbenches / Types
/ Resolution Functions Feb 14 Operators /
package std_logic_arith, numeric_std Feb 21
Microprocessor Structure A Case Study Feb 28
State Machines / Xilinx FPGA Implementation
Tips Mar 7 Mid-Term Exam Mar 14 Testbenches /
Integration of Embedded Microprocessors Mar 21
Spring Break Mar 28 Libraries, Subprograms Apr
4 Subprograms (cont) Procedures,
overloading Apr 11 TBD / Timing Analysis Apr
18 IP Apr 25 Project working session May 2
Projects Due / Demonstration perhaps short
final exam
9
Design Considerations for Digital Systems
ASIC Microprocessor NRE / Dev Cost
? Speed ? Flexibility ? Time to
Market ? Production Cost ?
What we'd like is the ability to be able to
implement something in hardware, but change it as
easily as changing software running on a
micro. The ideal hardware analogy would be the
ability to reconfigure the connection between
millions of transistors to compute a new function
for a new application
10
Traditional FPGA Architecture
Modules are connected by a Programmable
link. One-Time-Programmable Only
11
Actel Logic Elements
Combinatorial Module
Sequential Module
12
Xilinx Spartan Implementation
Configurable Logic Blocks are connected by
programmable interconnect, configuration of which
is controlled by SRAM unlimited reprogrammability
13
Configurable Logic Block
14
Programmable Logic Design Flow
Capture design Draw Schematic or use
HDL Compiler Translate VHDL to object code
usable by simulator. Check for
errors. Functional Simulation checks design
correctness by application of stimulus to design
and observation of output. Synthesis Maps and
optimizes design to fit into FPGA architecture
primitives Place / Route figures out where on
the FPGA/CPLD each primitive block goes, and how
to connect them together. Back Annotate / Timing
Simulation software creates a model of the
fully implemented design including
propagation/routing delays..etc. Design can then
be simulated to analyze for timing errors,
setup/hold violations and other
undesirables. Programming Using the output
from the FPGA design software, the connections on
the FPGA are physically created on the actual
chip. Now the device on the board will act like
the simulation. (The actual process is
architecture dependent)
15
VHDL Intro
Origins DOD began the specification of VHDL as
a solution to hardware procurement difficulties.
It was difficult to maintain designs and
second-source those designs if they got the
description of said designs in a proprietary
language. Languages weren't universally
supported Languages became obsolete Control given
to IEEE in 1986 for standardization. VHDL
VHSIC Hardware Description Language VHSIC Very
High Speed Integrated Circuits Through this
standardization, a functional description of a
digital circuit could be described in a way which
could be universally understood. VHDL '87 is the
first VHDL standard, with VHDL '93 being the
first revision among lots of software, '93 still
isn't even fully supported by lots of
tools. There is now a VHDL version of the
standard as well!
16
VHDL Modeling
Circuit complexity is such that designs cant be
completely analyzed Digital circuits are highly
parallel and not easily modelled by traditional
software. Simulation of our system is how we
verify. VHDL provides a convenient, universally
supported means to model circuit behavior.
17
Synthesis
In addition to being a powerful modeling
language, VHDL circuit descriptions can be used
by automated tools that can synthesize
(construct) hardware. Necessarily, this is a
subset of the entire VHDL. This subset will be
our focus for the majority of the
class Benefits TECHNOLOGY INDEPENDENT DESIGN!
(mostly...) migration to new FPGAs / CPLDs is
easier learning new design methodology is not
required Drawbacks People tend to think of
this as software and treat it as such. VHDL can
be difficult to read
18
Examples of VHDL Use
Early Project Verification VHDL system model
can be used to verify that a proposed system
design will work Subsystem design requirements
specification Detailed requirements for each
piece of the system can be formed with the aid of
the system model Synthesis models of some
pieces can be refined to be synthesizable and
thus easily built. Verification post-synthesis
vhdl models with timing can be inserted into the
system model and verified.
19
VHDL Entity Examples
entity my_circuit is port ( a in std_logic
b in std_logic c out std_logic ) end
my_circuit The entity simply describes the
name of the unit, its ports, and the types and
directions of those ports. A port is an entry
into or out of the design entity. Because the
port clause is optional, an entity declaration
may be written without declaring any ports. That
entity cannot communicate with other design
entities, but it can be simulated. We will always
have ports (with the exception of testbenches)
a
c
b
Another way
entity my_circuit is port ( a,b in
std_logic c out std_logic ) end my_circuit
20
Signal Values
IEEE 1164 standard defines nine values for a
digital signal '1' -forcing logic value 1 '0'
- logic value 0 U - uninitialized X - Forcing
unknown Z - High Impedance W - weak unknown L
- weak 0 H - weak 1 "-"' - don't care These
are implemented in the std_logic ennumerated type
(actually std_ulogic, but more on that in
lecture 3)
Metalogical Values
std_logic is sometimes referred to as MVL9
21
Port Mode

Identifies direction of data flow through the port

All ports must have an identified mode
IN
OUT
IN/OUT
BUFFER
Buffer addresses a typical problem in VHDL since
it is so strongly typed if you declare a signal
as out you may not read from it even if you
aren't really reading from the outside world.
22
Ex
entity dumb_circuit is port ( in1, in2, in3
in std_logic out1, out2 out
std_logic) end dumb_circuit out1 lt in1 and
in2 out2 lt out1 or in3
out1 is being read not allowed!
This is where mode buffer may be useful, if
out1 was declared in the entity as buffer
instead of out, there would be no error. This
causes other problems though, so in general, we
will avoid the use of the buffer mode, and find
other ways around this problem
23
Architecture
The entity describes the I/o of the device, the
architecture describes what it does/is.
the name of the entity for which you are
describing architecture
architecture my_architecture_name of my_circuit
is -- declarative section begin -- activity
statements end my_architecture_name
common practice is to put an entity/architecture
pair in a single file
24
Describing Architecture Structurally
Of what pieces is it composed, and how are they
connected?
a 4-bit shift register
the architecture is described by defining its
sub-elements and how they are put together.
25
Describing Architecture Structurally
CNT0
CNT1
CNT2
CLK
entity ctr3bit is port ( clk in std_logic
cnt0,cnt1,cnt2 out std_logic) end ctr3bit
a 3-bit synchronous counter
26
Describing Architecture Behaviorally
how does it respond to inputs, what do its
outputs do?
our 3-bit synchronous counter
clk
cnt2-0
000
001
010
011
100
101
110
111
111
Or, in words
The entity cnt3bit behaves in such a way that
each rising edge of the incoming clock, the
outputs cnt2-0 will update such that the next
value of cnt2-0 will be the previous value of
those outputs 1, where cnt0 is considered the
LSB, and cnt2 is considered the MSB of a 3-bit
unsigned binary number. Additionally, when our
output vector reaches 7 (111) it will wrap around
to 000 on the next clock.
27
Behavioral vs. Structural
VHDL supports both means of describing
architecture, and both means will be useful to
us. even in the same architecture

• code describing behavior is typically easier to
  understand.
• code describing behavior is generally easier to
  write
• hardware can be hidden
• code without low-level device specific modules is
  more portable.

• Some things lend themselves to structural
  description far more than behavioral
• code size can balloon out of control when you
  build schematics with a text editor
• Sometimes there is no alternative I.e. when
  your synthesizer wont take advantage of hw
  resources.

28
Ex Entity/Architecture Pair
in file my_circuit.vhd
library IEEE use IEEE.std_logic_1164.all entity
my_circuit is port ( a, b in std_logic
c,d out std_logic) end my_circuit
my_circuit
architecture behavioral of my_circuit is signal
andab std_logic begin c lt andab d lt not
andab andab lt a and b -- These are concurrent
assignments.. all happen at the same time end
behavioral
Note that this is the preferred solution to
problem mentioned earlier (as opposed to
declaring c as inout or buffer) since the
entity still indicates the true logical port
directions. lt is signal assignment Use and,
or, not, xor...etc. on std_logic types Included
in the IEEE.std_logic_1164 package
29
Conditional Signal Assignment
same syntax as regular signal assignment,
multiple branches allowed
y lt a when sel '0' else b
conditional_out lt a when sel1 '0'
else b
when sel2 '1' else a xor b when sel3
'0 else not b
Must end with unconditional else, since signal
must always have an assigned value regardless of
the inputs. Priority implied by syntax is REAL.
When no priority is needed, (i.e. Assignments are
mutually exclusive and dependent on a single
expression) use a selected signal assignment.
30
Conditional Signal Assignment
Zlt a when sel 1 else b when sel 0
else c Some synthesizers will be smart
enough to realize that conditions are
independent, (and give a warning) in this simple
example. As things get complicated, this is
nontrivial though, so you are the determiner of
what you want to synthesize.
sel
sel
a
c
z
b
31
std_logic_vector
std_logic_vector is simply an array where each
element is of type std_logic.
entity mux2x8 is port ( bus_a in
std_logic_vector(7 downto 0) bus_b in
std_logic_vector(7 downto 0) sel in
std_logic bus_out out std_logic_vector(7
downto 0)) end mux2x8
in the architecture, individual bits can be
referred to
bus_out(7) lt bus_a(7) when sel 0 else
bus_b(7)
the whole bus can be assigned to with a
bitstring literal
bus_out lt 11110000
or with other vectors
bus_out lt bus_a when sel 0 else bus_b
32
Selected Signal Assignment
entity dougs_ex is port (data in
std_logic_vector(3 downto 0) out_disp out
std_logic_vector(3 downto 0)) end dougs_ex
with data select out_disp lt 1001 when
0000, 0011 when 0001,
1101 when 0010, 1111
when 0011, 1100 when others
whats wrong here?
with sel select zlt a when '1', b when '0'
33
Structural VHDL
Helps break down a design into subsections for
ease of understanding, and design Instantiate
user defined models, or built-in macros that are
product specific (forfeit technology independence)
ROM
ALU
Instruction Decoder
34
Structural VHDL
given entity seg7_controller, which takes data in
and decodes it to turn it into a digit on a
7-segment display. We want to use this in
another design. How do we put it down and hook
it up?
The entity and architecture for seg7_controller
are in another file
architecture structure of some_top_level_design
is component seg7_controller Port (num
in std_logic disp out std_logic) end
component signal disp1_data, disp2_data
std_logic_vector (3 downto 0) signal
to_display_1, to_display_2 std_logic_vector (6
downto 0) begin dc1 seg7_controller port
map(disp1_data,to_display_1) dc2
seg7_controller port map (num gt disp2_data,
disp gt to_display_2) end structure
either way
35
Architecture review
entity simplecircuit is port ( a1,b1,a2,b2
in std_logic sigout out std_logic)) end
simplecircuit
architecture behavior of simplecircuit
is component and2 port (a, b in std_logic c
out std_logic) end component signal andout1,
andout2 std_logic begin U6 and2 port map
(a1,b1,andout1) U7 and2 port map
(a2,b2,andout2) sigout lt andout1 or
andout2 end behavior
declarative section
action statements
component instantiations
concurrent assignment
36
Lab Equipment
Xilinx Spartan 3 kit with Xilinx Spartan 3 FPGA
XC3S200-4FT256C
37
Spartan-3 Development Board
38
Software (get from Web!)
Xilinx WebPack Development Environment
PlaceRoute ModelSim XE Starter Edition
Simulator (a pared down version of the most
popular VHDL simulator)
Get the software online from http//www.xilinx.c
om/ise/logic_design_prod/webpack.htm
Some documents Board Users Guide
(UG130.pdf) http//www.xess.com/appnotes/webpack-6
_3-xsa.pdf This is a tutorial on using webpack
for another board design is similar to
lab1 very useful ignore board specific stuff,
and programming procedure (XSTOOLS) we use
IMPACT, which is builtin to wp