Introduction to FPGA Devices and Boards

1
Introduction to FPGA Devices and Boards
2
FPGA Devices
3
World of Integrated Circuits
Integrated Circuits
Full-Custom ASICs
Semi-Custom ASICs
User Programmable
PLD
FPGA
PAL
PLA
PML
LUT (Look-Up Table)
MUX
Gates
4
Two competing implementation approaches
FPGA Field Programmable Gate Array
ASIC Application Specific Integrated Circuit

• bought off the shelf
• and reconfigured by
• designers themselves

• designs must be sent
• for expensive and time
• consuming fabrication
• in semiconductor foundry

• no physical layout design
• design ends with
• a bitstream used
• to configure a device

• designed all the way
• from behavioral description
• to physical layout

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What is an FPGA?
Configurable Logic Blocks
I/O Blocks
Block RAMs
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Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in high volumes
Reconfigurability
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Other FPGA Advantages

• Manufacturing cycle for ASIC is very costly,
  lengthy and engages lots of manpower
• Mistakes not detected at design time have large
  impact on development time and cost
• FPGAs are perfect for rapid prototyping of
  digital circuits
• Easy upgrades like in case of software
• Unique applications
• reconfigurable computing

8
Major FPGA Vendors

• SRAM-based FPGAs
• Xilinx, Inc.
• Altera Corp.
• Atmel
• Lattice Semiconductor
• Flash antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.

Share over 60 of the market
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Xilinx

• Primary products FPGAs and the associated CAD
  software
• Main headquarters in San Jose, CA
• Fabless Semiconductor and Software Company
• UMC (Taiwan) Xilinx acquired an equity stake in
  UMC in 1996
• Seiko Epson (Japan)
• TSMC (Taiwan)

ISE Alliance and Foundation Series Design
Software
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Xilinx FPGA Families

• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not
  recommended for modern designs.
• High-performance families
• Virtex (0.22µm)
• Virtex-E, Virtex-EM (0.18µm)
• Virtex-II, Virtex-II PRO (0.13µm)
• Virtex-4 (0.09µm)
• Low Cost Family
• Spartan/XL derived from XC4000
• Spartan-II derived from Virtex
• Spartan-IIE derived from Virtex-E
• Spartan-3

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Xilinx FPGA Block Diagram
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CLB Structure
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CLB Slice Structure

• Each slice contains two sets of the following
• Four-input LUT
• Any 4-input logic function,
• or 16-bit x 1 sync RAM
• or 16-bit shift register
• Carry Control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
• Storage element
• Latch or flip-flop
• Set and reset
• True or inverted inputs
• Sync. or async. control

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LUT (Look-Up Table) Functionality

• Look-Up tables are primary elements for logic
  implementation
• Each LUT can implement any function of 4 inputs

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5-Input Functions implemented using two LUTs

• One CLB Slice can implement any function of 5
  inputs
• Logic function is partitioned between two LUTs
• F5 multiplexer selects LUT

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5-Input Functions implemented using two LUTs
OUT
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Distributed RAM

• CLB LUT configurable as Distributed RAM
• A LUT equals 16x1 RAM
• Implements Single and Dual-Ports
• Cascade LUTs to increase RAM size
• Synchronous write
• Synchronous/Asynchronous read
• Accompanying flip-flops used for synchronous read

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Shift Register

• Each LUT can be configured as shift register
• Serial in, serial out
• Dynamically addressable delay up to 16 cycles
• For programmable pipeline
• Cascade for greater cycle delays
• Use CLB flip-flops to add depth

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Shift Register

• Register-rich FPGA
• Allows for addition of pipeline stages to
  increase throughput
• Data paths must be balanced to keep desired
  functionality

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Carry Control Logic
COUT
YB
Look-Up Table
Carry Control Logic
Y
G4 G3 G2 G1
S
D
Q
O
CK
EC
R
F5IN
BY SR
XB
Look-Up Table
Carry Control Logic
X
S
F4 F3 F2 F1
D
Q
O
CK
EC
R
CIN CLK CE
SLICE
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Fast Carry Logic

• Each CLB contains separate logic and routing for
  the fast generation of sum carry signals
• Increases efficiency and performance of adders,
  subtractors, accumulators, comparators, and
  counters
• Carry logic is independent of normal logic and
  routing resources

MSB
Carry Logic Routing
LSB
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Accessing Carry Logic

• All major synthesis tools can infer carry logic
  for arithmetic functions
• Addition (SUM lt A B)
• Subtraction (DIFF lt A - B)
• Comparators (if A lt B then)
• Counters (count lt count 1)

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Block RAM

• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 104 memory blocks
• 18 kbits 18,432 bits per block
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs

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Spartan-3 Block RAM Amounts
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Block RAM Port Aspect Ratios
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Block RAM Port Aspect Ratios
1
2
4
0
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
81
0
2k x (81)
2047
162
0
1024 x (162)
1023
16,383
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Dual Port Block RAM
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Dual-Port Bus Flexibility
RAMB4_S4_S16
WEA
Port A Out 18-Bit Width
Port A In 1K-Bit Depth
ENA
RSTA
DOA170
CLKA
ADDRA90
DIA170
WEB
Port B Out 9-Bit Width
Port B In 2k-Bit Depth
ENB
RSTB
DOB80
CLKB
ADDRB80
DIB150

• Each port can be configured with a different data
  bus width
• Provides easy data width conversion without any
  additional logic

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Two Independent Single-Port RAMs
RAMB4_S1_S1
Port A In 8K-Bit Depth
Port A Out 1-Bit Width
VCC, ADDR120
Port B In 8K-Bit Depth
Port B Out 1-Bit Width
GND, ADDR120

• To access the lower RAM
• Tie the MSB address bit to Logic Low
• To access the upper RAM
• Tie the MSB address bit to Logic High

• Added advantage of True Dual-Port
• No wasted RAM Bits
• Can split a Dual-Port 16K RAM into two
  Single-Port 8K RAM
• Simultaneous independent access to each RAM

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New 18 x 18 Embedded Multiplier

• Fast arithmetic functions
• Optimized to implement multiply / accumulate
  modules

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18 x 18 Multiplier

• Embedded 18-bit x 18-bit multiplier
• 2s complement signed operation
• Multipliers are organized in columns

Note See Virtex-II Data Sheet for updated
performances
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Basic I/O Block Structure
D
Q
Three-State
EC
FF Enable
Three-StateControl
Clock
SR
Set/Reset
D
Q
Output
EC
FF Enable
Output Path
SR
Direct Input
FF Enable
Input Path
D
Q
Registered Input
EC
SR
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IOB Functionality

• IOB provides interface between the package pins
  and CLBs
• Each IOB can work as uni- or bi-directional I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed

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Routing Resources
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Clock Distribution
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Spartan-3 FPGA Family Members
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FPGA Nomenclature
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Device Part Marking
Were Using XC3S100-4FG256
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Using Library Components in VHDL Code
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RAM 16x1 (1)

• library IEEE
• use IEEE.STD_LOGIC_1164.all
• library UNISIM
• use UNISIM.all
• entity RAM_16X1_DISTRIBUTED is
• port(
• CLK in STD_LOGIC
• WE in STD_LOGIC
• ADDR in STD_LOGIC_VECTOR(3 downto 0)
• DATA_IN in STD_LOGIC
• DATA_OUT out STD_LOGIC
• )
• end RAM_16X1_DISTRIBUTED

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RAM 16x1 (2)

• architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of
  RAM_16X1_DISTRIBUTED is
• attribute INIT string
• attribute INIT of RAM16X1_S_1 label is "F0C1"
• -- Component declaration of the
  "ram16x1s(ram16x1s_v)" unit
• -- File name contains "ram16x1s" entity
  ./src/unisim_vital.vhd
• component ram16x1s
• generic(
• INIT BIT_VECTOR(15 downto 0) X"0000")
• port(
• O out std_ulogic
• A0 in std_ulogic
• A1 in std_ulogic
• A2 in std_ulogic
• A3 in std_ulogic
• D in std_ulogic
• WCLK in std_ulogic
• WE in std_ulogic)
• end component

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RAM 16x1 (3)

• begin
• RAM_16X1_S_1 ram16x1s generic map (INIT gt
  X"F0C1")
• port map
• (OgtDATA_OUT,
• A0gtADDR(0),
• A1gtADDR(1),
• A2gtADDR(2),
• A3gtADDR(3),
• DgtDATA_IN,
• WCLKgtCLK,
• WEgtWE
• )
• end RAM_16X1_DISTRIBUTED_STRUCTURAL

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RAM 16x8 (1)

• library IEEE
• use IEEE.STD_LOGIC_1164.all
• library UNISIM
• use UNISIM.all
• entity RAM_16X8_DISTRIBUTED is
• port(
• CLK in STD_LOGIC
• WE in STD_LOGIC
• ADDR in STD_LOGIC_VECTOR(3 downto 0)
• DATA_IN in STD_LOGIC_VECTOR(7 downto 0)
• DATA_OUT out STD_LOGIC_VECTOR(7 downto 0)
• )
• end RAM_16X8_DISTRIBUTED

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RAM 16x8 (2)

• architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of
  RAM_16X8_DISTRIBUTED is
• attribute INIT string
• attribute INIT of RAM16X1_S_1 label is "0000"
• -- Component declaration of the
  "ram16x1s(ram16x1s_v)" unit
• -- File name contains "ram16x1s" entity
  ./src/unisim_vital.vhd
• component ram16x1s
• generic(
• INIT BIT_VECTOR(15 downto 0) X"0000")
• port(
• O out std_ulogic
• A0 in std_ulogic
• A1 in std_ulogic
• A2 in std_ulogic
• A3 in std_ulogic
• D in std_ulogic
• WCLK in std_ulogic
• WE in std_ulogic)

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RAM 16x8 (3)

• begin
• GENERATE_MEMORY
• for I in 0 to 7 generate
• RAM_16X1_S_1 ram16x1s generic map (INIT gt
  X"0000")
• port map
• (OgtDATA_OUT(I),
• A0gtADDR(0),
• A1gtADDR(1),
• A2gtADDR(2),
• A3gtADDR(3),
• DgtDATA_IN(I),
• WCLKgtCLK,
• WEgtWE
• )
• end generate
• end RAM_16X8_DISTRIBUTED_STRUCTURAL

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ROM 16x1 (1)

• library IEEE
• use IEEE.STD_LOGIC_1164.all
• library UNISIM
• use UNISIM.all
• entity ROM_16X1_DISTRIBUTED is
• port(
• ADDR in STD_LOGIC_VECTOR(3 downto 0)
  
• DATA_OUT out STD_LOGIC
• )
• end ROM_16X1_DISTRIBUTED

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ROM 16x1 (2)

• architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of
  ROM_16X1_DISTRIBUTED is
• attribute INIT string
• attribute INIT of ROM16X1_S_1 label is "F0C1"
• component ram16x1s
• generic(
• INIT BIT_VECTOR(15 downto 0) X"0000")
• port(
• O out std_ulogic
• A0 in std_ulogic
• A1 in std_ulogic
• A2 in std_ulogic
• A3 in std_ulogic
• D in std_ulogic
• WCLK in std_ulogic
• WE in std_ulogic)
• end component
• signal Low std_ulogic 0

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ROM 16x1 (3)

• begin
• ROM_16X1_S_1 ram16x1s generic map (INIT gt
  X"F0C1")
• port map
• (OgtDATA_OUT,
• A0gtADDR(0),
• A1gtADDR(1),
• A2gtADDR(2),
• A3gtADDR(3),
• DgtLow,
• WCLKgtLow,
• WEgtLow
• )
• end ROM_16X1_DISTRIBUTED_STRUCTURAL

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XESS Board
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External Connections to XSA Board
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Arrangement of Components
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XSA Board Connectivity
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100 MHz Programmable Oscillator
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Experiment 3 Introduction
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Questions?