IspLEVER 6.1 ? ??? ?? ??(VHDL)

1
IspLEVER 6.1 ? ??? ?? ??(VHDL)
2
Table of Contents
ispLEVER 6.1
1 ??? Project ??? 2 Device ???? 3 Design
Source ??? 1) Schematic Design Example
2) Design ??? ?? 3) 4-bit counter ?? 4)
Compile 5) ??? ? ?? 5 1) Package
View 5 2) Spreadsheet View 6)
Simulation 6 1 Test Bench File ???
6 2 Simulation ?? 6 3 ModelSim
3
Lattice Device? Design (VHDL)
1 ??? Project ???
?? ??? schematic??? ???? ???.
File-gtNew Project? ??
Project?.syn?? ???? project name? Design Entry
Type? Synthesis Tools? ???? ??(N) ??? ???
ABEL/Schematic VHDL/Schematic Verilog/Schematic? ?
?Design ??
4
Lattice Device? Design (VHDL)
2 Device ????
Device ???? Family -gt Device -gtSpeed grade -gt
Package type -gtOperating conditions Device
??? ???? ??(N)? ??
Add Source -gt??? ??? source ??? ?? ?? ???
????? ??? ? ?? -gt?? ??? ??? ?? ??? project?
?? ??? ? ??? ??(N) ? ???? Project
Information -gt???? ??? ???? ??? ???
5
Lattice Device? Design (VHDL)
???? ???? ??? ??? ?? ??? PATH? ???? ????? ???
??. Source in Project??? Untitled?? ?? ??
??? ??? ??????? ??? ?? ?? ? ??.(????)
LFEC1E-3T100C ????? ???? ???? ???, ? ??? ????
?? ?? ??? ???? Device Selector? ??? ??. Device
Selector, ? ????? ??? ????? ?? ?? ????? ??? ??.
6
Lattice Device? Design (VHDL)
3 Design Source ???
1) Schematic Design Example
NEW -gt??? source??? Import -gt??? ??? source?
????
Source -gtNew ??
2) Design ??? ??
ABEL Test Vectors -gtABEL? Design? ?? Simulation
?? ?? Text Editor Schematic -gtSchematic? ???
Design VHDL Module -gtVHDL Editor Waveform
Stimulus -gtSimulation? Waveform Editor
7
Lattice Device? Design (VHDL)
-gtVHDL Module? ???? ?? TEXT ?? ???? File,
Entity ? Architecture Name? ???? ?? ???.
??? ??? ???? ??? ?? ??. -gt?? File
Name? ?? ???? ???? ?? ?? Entity name ?
file name?? architecture name ? Behavioral?
???? ??? ??.
library ieee use ieee.std_logic_1164.all use
ieee.std_logic_arith.all use ieee.std_logic_unsig
ned.all entity demo is end architecture
behavioral of demo is begin end behavioral
8
Lattice Device? Design (VHDL)
3) 4-bit counter ??
?? ??? ?? 4-bit up counter? ??? ??? ??
9
Lattice Device? Design (VHDL)
4) Compile
??? ??? ?, ???? ?? ??? ????? ???? ??? ??? ?? ? ?
??. ?? VHDL? syntax check? Synthesis? ?? ???
Compile EDIF File??. ?? ???? ??? ?????. ( ???
??? ?? ???? ?? ? ??? ???? ?? ?? VHDL? ?? ? ????
??? ???? ??. ???? ?? ???? ?? Compile EDIF File?
???? ?? ??? ??.)
Process state Icon
Initial No icon
Warnings
completed
Errors
10
Lattice Device? Design (VHDL)
5) ??? ? ?? -gt Design Planner (post-Map)? ??
??? ? ?? CPLD device
Constraint Editor? ?? FPGA device Design
Planner (post-Map)? ??
View ??? ???? ?? ?? ??? view? ???? ??? ??? ??? ?
??. ? ??? ?? ?? ???? ?? Package View? Spreadsheet
View ? ?? ??? ??? View??? ???? Package
View ??? ????.
11
Lattice Device? Design (VHDL)
5 1) Package View
Package View? ???? ?? ???? Package ??? ???? ???
??? ????? ???? ????? ? I/O? ???? ??? ?? ????.
??? pin? ????? ? ??? Top View? pin?? ??? ??? ???
?? Unlock? click?? ??
(signal? ??? ? datasheet? Pinout
Information? ??? ??)
12
Lattice Device? Design (VHDL)
5 2) Spreadsheet View
??? pin Attributes?? pin block? Double click? ?
?? ????? pin? ???? Bank? ???? ?? ????.
?? pin??? ??? ??? ??? ??? demo.lpf ??? ????.
13
Lattice Device? Design (VHDL)
6) Simulation
6 1 Test Bench File ???
Mentor? Model Sim? ???? Simulation ?? ???? Test
Bench File? ???? ??. Test Bench File ??? ???
VHDL Test Bench Template? ???? ?? ??? ?? Test
Bench Format? ???? ??. ?? ??? cnt.vht? ?????.

14
Lattice Device? Design
-gt Text Editor? ??? ??
Window ???? Text Editor ??? ???? Text Editor?? ??.
Text Editor??? File -gt New ??
15
Lattice Device? Design (VHDL)
??? ?? ??? cnt.vht??? Drag?? ??? ?? ? ???? ?? ??
input wave stimulus? ?? ??? ??.
Clock ???, clear ???
Clock ? Clear ?? ??
?? ??? ?? Test Bench? ????. (Test bench? ??
???? VHDL??? ??)
Test Bench File? ?????? ? ??? ?? .vhd? File
Name? ??? OK? ??
16
Lattice Device? Design (VHDL)
?
Test Bench File? ???? ?? ?? ??? ?? File? Import??.
?
?
?
Importing?? ?? Associate VHDL Test Bench?? ???,
? ??? ?? Function Simulation? ? ???? ????? ????,
???? Timing? Function Simulation? ?? ? ???? ??
???? Device? ???? ??.
17
Lattice Device? Design (VHDL)
6 2 Simulation ??
??? Sources in Project??? Test Bench File? ????
VHDL Functional Simulation (??? Function?
??) VHDL Post-Route Functional Simulation VHDL
Post-Route Timing Simulation (?? ?????? ???
Delay?? ??) ? ??? Simulation??? ????
Simulation? ???? ???? ??
Simulation??? ???? ?? ? ??? ?? ModelSim??? ????
??.
18
Lattice Device? Design (VHDL)
6 3 ModelSim
Command?? ??? ???? Run? ????? Wave?? ???? ??? ? ??
??? Clear ???