EMU Front-end Electronics T.Y. Ling March 5, 1998

1
DMB Production
8-layer PC Board, 2 Ball-Grid Array FPGAs, 718
Components/Board
550 Production Boards
2
DMB Production Boards

• 411/550 boards delivered/tested
• 70 boards required repair

Board are being boxed and stored until needed at
Ohio State
Production Schedule
3
New Crate Controller Development

• A VMEbus Controller with Gigabit Ethernet
• A custom board designed and developed at OSU
• Based on XILINX Virtex-II Pro
• Custom firmware.
• Optical transceiver (for Gbit Ethernet)
• Communicates with stand-alone PC (in USC55) via
  Gigabit Ethernet

Its Alive !
Measured Continuous Read/Write VME Transfers at
120 Mbit/s
4
Gigabit-VME Ethernet Protocol
Utilize Commercial Software (Drivers)
Ethernet Raw Socket Layer (requires setuid())
Packet to Controller
Ethernet Header Private
Protocol Header VME Write 1
VME Read 2 VME
Delay 3 VME Write 4
PktType NVME
Cntrl VME Addr Data
Cntrl VME Addr
Cntrl VME Delay
Cntrl VME Addr Data
Dest Addr SRC Addr PktLen
???
14 bytes
4 bytes 8 bytes
6 bytes
4 bytes 8 bytes

Packet from Controller
Ethernet Header
Private Rcv. Header Data
from VME
Dest Addr SRC Addr PktLen
PktType RSVD NWrds
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
???
14 bytes
6 bytes 2
bytes 2 bytes

Note Jumbo Packet Support 9000 bytes
5
Controller Production Schedule
New Controller has Run in DDU/DCC Crate for 1
Month - Very Stable, No Bus Hangs or Resets
Needed Yet! - 2nd prototype/preproduction
board TBD (some changed components,
layout fixes, and form factor change) -
Radiation Tests Need to be Performed Firmware
Additions Needed - Storage of MAC Address
in Flash RAM - Controller Handshake for
Overflow Protection - JTAG interface for
reprogramming PROM via ethernet
Production Schedule
6
DDU Prototype

• Functions
• Merge data from 13 DMBs
• Perform error checking and status monitoring
• (CRC, word count, L1 number,
  BXN, overflow, link status)
• Communicates w/FMM
• Large Buffer Capacity
• 2.5 MB buffer
• Average DDU data volume estimated to be 0.4kB per
  L1A at LHC (_at_1034 lumi)
• Buffer can hold over
  6000 events
• TTC signals from DCC
• Slow control via VME

7
DCC Prototype

• Data Concentration
• Merge data from 9 DDUs
• send merged data to central DAQ via 1 or 2 SLINKs
  
• Has two optional GbE spy data path
• Fast Control
• Receive TTC fiber signals using TTCrx,
• Fanout L1A, LHC_clock and other TTC signals to
  DDUs
• Has optional FMM interface

8
DDU/DCC Prototype
DDU/DCC TestBeam 2004 - very
successful, no problem for gt 10x LHC rate
Both DDU/DCC Passed ESR Nov. 2004
DDR FIFO bit errors bad chip used on
DDU/DCC/Controller (72T40/20 family)

• IDT72T40118, 40-bit 0.5MByte, DDR FIFO bit
  errors, esp. bit 21
• Detailed test on test board
• Error shown on DDU and VME_controller (DDR FIFO)
• Still working with IDT
• Replacement
• TI SN74V3690
• IDT 72V36110

FIFO
Qout3920
LFSR parity
COMP
D3920
Q3920
Din190
Qout190
Q190
D190
FIFO Write/read
Error report
9
DDU/DCC Production
Relayout Both DDU and DCC
Production Schedule
( pre-production boards)