Analog Digital VLSI Design Reference Current Voltage

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Analog Digital VLSI DesignReference Current /
Voltage
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Reference voltage/ current
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Requirements
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Characteristics
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Sensitivity
gain
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Sensitivity
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How to generate bias current?

• Generate stable Vref directly
• Generate stable Iref, use it to generate voltage
• Generate stable Iref, and mirror it.

Vref
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References
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Passive reference voltage gen. ckts.
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Active referencesvgs referenced
Vref 1/3 Vdd 1/ 3 Vds S 1
Not much gain
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Vgs referenced
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Another approach
v1
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Iout is not independent of variations in Vdd
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Cascoding
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Modified Vgs referenced
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Vbe referenced
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Modified Vbe referenced
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Observations

• Sensitivity of the voltage across an active
  device can be less than 1
• How to design a Vref/ Iref independent of Vdd?

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Self bias

• Generate Vref across an active device
• Using Vref generate a current Iout
• Use Iout to force the current into the reference
  active device

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Concept
Forces Iin decided by Iout
Iin
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Current dec.
If vdd increases, current tend to increase
Voltage reduces
Node voltage increases more to inc. the current
Node voltage decreases Current rolls back
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Vdd insensitive

• Self bias circuit
• But it is not temperature insensitive

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Cascoding improves sensitivity
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Temperature insensitivity measure
Example
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• Now we modify self bias to force a unique current
• 3 methods
• Using R
• Using BJT
• Using MOS
• For we will compute Tcf, vddS vref

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Force a desired current using R
This loop will always try to negate variations
in Vdd
Modification to force a unique current
Vdd independent But process and temperature
dependent K should be gt1
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Tcf
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Sensitivity to Vdd
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Make L large
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Start up problem
Initially Vdd
Conducts initially As Vx increases, M5 stops
conducting
vX
Initially gnd
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Remarks

• Vref Vgs1- Vgs2
• Can we make Vref a Vgs1?
• Can we have K1?

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Using MOS - Vt referenced K1
earlier Vref difference of two Vgs.
Loop to stabilize current But Bias is required,
shd. come from reference arm Now M2 becomes
redundant as M5 makes M1 diode connected So,
remove M2
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Self bias- Vt referenced
Start up circuit
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Vdd sensitivity
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sensitivity Calculation
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Tcf
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Using BJT--Vbe referenced
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Vbe referenced in CMOS
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Vbe referenced in CMOS
CTAT CURRENT
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Tcf calculations
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calculation
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Vth referenced self bias
PTAT CURRENT Is becomes n times
Shd. Be equal
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Another circuit
Ckt to make x , y node voltages equal
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Temp insensitive reference

• Can we add PTAT and CTAT current to get temp
  insensitive reference?

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So, two ways
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Temp insensitive Reference voltage
Vref
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Temp. plot
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Cascoding
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Vref to Iref conversion
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Better compensation
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Performance Obtained
The Performance achieved by the circuit is as
follows
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Temperature Sweep
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All mos CURRENT reference
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CONCEPT
Vt temp dependence
Negative constants
µ temp dependence
Drain current
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,Obtain Vgs
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Vov. dominated
Mobility dominated
Choose 2 Vgs on both sides of ZTC point
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Operation
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Core circuit
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Temperature insensitive
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Vbe referencedBJT only
Thermal voltage 25 mV
Iin Iout
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