Device Modeling and Simulation for VLSI Design Robert W. Dutton Stanford University

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Device Modeling and Simulationfor VLSI
DesignRobert W. DuttonStanford University

• Introduction--TCAD
• Moores Law Scaling using TCAD
• Intrinsic Devices
• Isolation (and other Parasitic) Effects
• Kinds of Modeling
• Technology Design (Scaling and SPICE Files)
• Behavior Modeling (ESD, RF Substrate Coupling)
• Future Scaling Issues
• Transition to SyCaMore Project

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Technology Computer-Aided DesignTCAD
Extrinsic (and Layout)
Intrinsic (active/passive devices)
Circuit
Technology Files
Masks
Device
Interconnects
Characterization
Process
Isolation
Device Scaling
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EDA/TCAD Boundaries
(EDAElectronic Design Automation)
Circuit Design Verification
ECAD
SPICE Models
IC Layout
Extraction ERC
Behavior Models
TCAD
Process Technology
Device Interconnect Design
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Transistor Scaling versus Year--Moores Law
Gate Length (L) decreases with each technology
generation Density of gates doubles with
each generation Cost per transistor
is reduced ( 1/Density)...
0.4 0.3 0.2 0.1 0.0

Density of IC devices is doubling with each
new generation
Gate Length (mm)


Gordon Moore

1995
2000 2005
2010
Year
Figure 1
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Robert Dutton, Fairchild Fellow (Cal gEEk,
circa-1967)
Moore Dutton Grove
Figure 2
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Moores Law and Scaling (what are the limits?)
Growing demands on Equipment side
0.4 0.3 0.2 0.1 0.0
Wavelength at 193 nm
Gate Length (mm)
Actual Oxide Atoms
100 nm
Growing challenges on Materials side

1995
2000 2005
2010
Year
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IC Scaling Issues--Front-End, Back-End
Substrate

• Back-End Simulation
• Multi-layer materials
• Electro-Thermal

• Intrinsic Devices
• Junctions
• Contacts
• Dielectrics

• Substrate Engineering
• Parasitics
• Packaging

Need for New, Faster, Smaller Transistors
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TCAD-based Model Extraction (for SPICE)
Simulations (and Measured Data) of I-V, C-V and
transient behavior of Scaled Devices
TCAD
T C A D
Extraction of key SPICE parameters for compact
models (i.e. MOS level 3, BSIM) that are the
technology file used for circuit design.
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Scaling Effects in MOS--Quantum Mechanical Limits
tox21A
tox15A
Vg0

• MOS C-V and gate current
• Classical for gt20Angstroms
• Tunneling through gate--
• Changes C-V
• Gate current BIG problem

Log Ig
tox15A
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Challenges on the Road Ahead
100 nm
There are a range of physical, chemical
and materials changes as IC technology moves
into the sub 100 nm regime
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Future Scaling Issues

• Intrinsic Devices
• Thin oxides
• High-??dielectrics
• Dopant Statistics
• Alternatives (single electron, pillars,
  heterojunctions...)
• Extrinsic Devices
• Trenches
• Materials (metals, Low-??...)
• Stress
• Alternatives (free space, flip-chip, use of
  MEMS...)

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Challenges at Atomic Scale(21st Century TCAD and
MOS Scaling Limits)
Fundamental Changes
Atomic Scales New Materials Beyond
Planar Pillars 3D devices Nano-tubes . . .
Honto ni chisaku natte ne!
(or in English) Things are really getting small!
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Synthesized Compact Models (SyCaMore)
for Mixed Signal Design and Noise
Analysis Robert Dutton Stanford University
Karti MayaramOregon State University

• Introduction
• Highlights Project Status
• Algorithms and Model Generation
• Test Circuits for Model Validation
• Plans

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What is the substrate noise problem?why is it
important?

• Atheros
• Interest in single-chip integration issues
• Using state-of-the-art foundry technology

(Atheros, ISSCC 2002, Paper 7.2)
Digital blocks represent most of the chip they
generate LOTS of switching noise
The radio has very sensitive analog (RF) blocks
that dont like noise!!
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Introduction--RF/Mixed-Signal Noise Coupling

• Noise spectra and coupling mechanisms depend on
• Circuit configurations--including layout
  technology
• Distributed device effects
• Substrate behavior (including nonlinear effects)

Phase Noise means that frequency of VCO is not
exact (system problem)
VCO Phase Noise
Frequency
Frequency
Digital Block
VCO
Noise couples via transistor bulk regions (gmb)
Substrate Transfer Function
Focus of the SyCaMore Project
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Oscillations and Voltage-Controlled Oscillators
Feedback perspective Aa/(1-af), if af1 we get
infinite gainor oscillations From EE 122 the
phase-shift oscillator specifically uses
series-parallel RC network to Make f1/a
and Guarantee exact 0-degree phase
shift Timing-based oscillations--this can be
ring oscillator type or charge-discharge (of
Capacitance) type
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Example of Phase-Shift Oscillator (EE122)
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Basics of Timing-based Oscillators

• Timer Circuits
• Schmitt Trigger
• 555 IC
• Many others...

x is the portion of the total period for which
the respective Ix is in control
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Making a Voltage-Controlled (Ring) Oscillator
Basic Point Frequency of Oscillations directly
proportional to the Current (Ix) which in turn is
Controlled by a Voltage (see previous slide about
timing)
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A word about PLLs (and role of VCO)
Key Objective of Phase-Locked Loop Use the
phase comparator block (X) to keep red VCO
doing exactly what the incoming signal is doing.
This can either a) guarantee clock
synchronization or b) demodulate FM signals
(coming from green).
fi
n-to-f
ni
no
fosc
VCO
Input voice signals
ni
no
VCO
Output FM-modulated signals
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Test Structures--Create Digital Noise Emulation
(DNE) blocks and study the effect of digital
noise on Phase-Locked Loops (PLLs)
Hardware Version of DNE

• Simulation
• Verify noise behavior
• Parameterize DNEs

• Power-Current profiles
• Bluetooth (Atheros)
• Multiple Freq. Synth. (IBM)

Programmed Digital Noise Emulator

• Test Chip Implementation
• Programmed DNE (parameterized based on digital
  application domain)
• Suitable RF/Analog block(s)

(Atheros, ISSCC 2002, Paper 7.2)
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Modeling Digital Noise --how does digital noise
get modeled, both in time and frequency domains
Power Information (-gtCurrent Spikes)
inputs
Aggregation of block-level currents, based on
power estimates, provides parameters of current
injection. Transform to frequency-domain give
good measure of noise spectrum.
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Current Noise Models--simulation and mathematical
What happens when a CMOS gate switches?

• Objective Create mathematical model for current
  noises on supply rails.
• Basic concept
• Inoise(t)Id,sat1(fitted curve for transition
  curve of switch)2
• 1 the quadratic model for simplification.
• 2
• Example
• Current noise in the supply of an inverter with
  trisetfall400ps
• Red Mathematical model
• Blue SPICE simulation

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Behavior simulation--PLL with digital noise(flow
chart of models, tools and key results)
VCO
Substrate Network Noise Injection
(lumped model) Circuitry

• Noise Model
• Frequency of the inverter switching, 17MHz
• PLL
• Reference frequency 150MHz
• Center Frequency 4.5GHz
• Sampling time 100ps
• Results
• Even and Odd harmonics of 17MHz observable with
  different amplitudes.

Heres simulations of PLL frequency response
based on substrate noise coupling
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Modeling Distributed Substrate Effects--coupled
simulation (including automated extraction of
models)
w1
VOUT RL
Vdd
numerical (2D) substrate model

• Plug-and-Play with Device Simulators
• New materials
• New classes of devices and physical coupling
  effects

w2

• Automated Extraction
• Maintain physical mapping and technology
  dependencies
• Allows parameterization based on layout details

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A Simple Example--CODECS Simulations(two-tone
results complete device and resistor-lumped
model)
one-lump R

• Using two frequencies w1 (gate) and w2
  (substrate) what are the observed tones at
  VOUT?
• Additional tones mean that there are nonlinear
  (distortion effects)
• Differences between complete 2D device level and
  lumped model means distributed effects are
  important

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Simulation Results-- MOSFET Substrate Noise
One-lump resistive model for substrate
Numerical model for substrate
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Frequency Domain Spectrum -- (substantial
differences between full numerical and lumped
substrates)
1MHz
1KHz
2MHz
2KHz
3MHz
Input Signal
Substrate Signal
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Modeling of Substrate Parasitics--a more
detailed study of topological effects
Numerical Model
Two Alternative Models For Substrate Resistor

• Rsub from numerical simulation of the lateral
  portion of substrate

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Two-tone CODECS Analysis --First Model
5V
D
G
B
S
distributed lumping
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Oscillator Jitter--Simulations and Analysis
(comparisons of symmetric versus asymmetric noise
injection)

• Spectre time domain simulations and HL analysis
  for uncorrelated substrate noise injection show
  jitter peaks at
• n?0 (for asymmetric)
• 5n?0 (for symmetric)

HL--Hajimiri and Lee, The Design of Low Noise
Oscillators, Kluwer Academic Press, 1999
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Model Generation--Synthesized Compact Models
(SCMs) for the Substrate Effects

• Lumped (SCM) Network
• Physical-based topography number of lumps
  frequency dependent
• Layout dimensions used to scale resistor
  provides bi-directional link

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Time to Summarize

• Simulations and (TCAD) Modeling are useful for
  Scaling ICs--Moores Law and Beyond
• Basic Transistor behavior (including technology
  scaling)
• Extracting SPICE models
• Understanding Parasitic Effects
• Substrate Noise Coupling is Key Challenge for
  future System-on-Chip (SoC) Integration
• Analog blocks are very sensitive (especially RF
  components)
• Modeling of substrate coupling involves TCAD-,
  SPICE- and Behavior-Level representations
• Thanks REUs!!
• Justin
• Jason
• Jiambo
• Qi

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Where Ill be Aug. 18-23, 2002
Were Too little!
Dinner!