An Introduction to VLSI Very Large Scale Integrated Circuit Design: circuit functionality perspectiv

1
An Introduction to VLSI (Very Large Scale
Integrated) Circuit Designcircuit
functionality perspective
Presented at ECE1001Nov 9th, 2006
2
Basic IC circuit component transistor
First transistor Bell Labs, 1948
3
Intel 4004 Micro-Processor
1971 1000 transistors 1 MHz operation
4
Intel Pentium (IV) microprocessor
2002 35 Million transistors 1 GHz
operation 0.18µm technology
5
Intel Core2 Duo Processor
2006 gt100 Million transistors 2 GHz
operation 65nm technology
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Moores Law

• In 1965, Gordon Moore noted that the number of
  transistors on a chip doubled every 18 to 24
  months.
• He made a prediction that semiconductor
  technology will double its effectiveness every 18
  months

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Moores law in Microprocessors
Transistors on Lead Microprocessors double every
2 years
1000
2X growth in 1.96 years!
100
10
P6
Pentium proc
Transistors (MT)
486
1
386
286
0.1
8086
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Courtesy, Intel
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Frequency
10000
Doubles every2 years
1000
P6
100
Pentium proc
Frequency (Mhz)
486
386
10
8085
286
8086
8080
1
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2
years
Courtesy, Intel
9
Power Dissipation
100
P6
Pentium proc
10
486
286
8086
Power (Watts)
386
8085
1
8080
8008
4004
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Courtesy, Intel
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Power will be a major problem
100000
18KW
5KW
10000
1.5KW
500W
1000
Pentium proc
Power (Watts)
100
286
486
8086
10
386
8085
8080
8008
1
4004
0.1
1971
1974
1978
1985
1992
2000
2004
2008
Year
Power delivery and dissipation will be prohibitive
Courtesy, Intel
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Power density
10000
1000
Power Density (W/cm2)
100
8086
10
4004
P6
8008
Pentium proc
8085
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low
temp
Courtesy, Intel
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Not Only Microprocessors
CellPhone
Digital Cellular Market (Phones Shipped)
(data from Texas Instruments)
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Design Abstraction Levels
SYSTEM
MODULE

GATE
CIRCUIT
DEVICE
G
D
S
n
n
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The MOS Transistor
Polysilicon
Aluminum
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What is a Transistor?
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MOS Transistors -Types and Symbols
D
D
G
G
S
S
Depletion
NMOS
Enhancement
NMOS
D
D
G
G
B
S
S
NMOS with
PMOS
Enhancement
Bulk Contact
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Threshold Voltage Concept
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Transistor Model for Manual Analysis
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The CMOS Inverter A First Glance
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CMOS Inverter
N Well
PMOS
2l
Contacts
Out
In
Metal 1
Polysilicon
NMOS
GND
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Two Inverters
Share power and ground Abut cells
Connect in Metal
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CMOS InverterFirst-Order DC Analysis
DD
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DC OperationVoltage Transfer Characteristic
VOH f(VOL) VOL f(VOH) VM f(VM)
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Mapping between analog and digital signals
V

1

OH
V
IH
Undefined
Region
V
IL

0

V
OL
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Definition of Noise Margins
"1"
V
OH
Noise margin high
NM
H
V
IH
UndefinedRegion
V
NM
Noise margin low
L
IL
V
OL
"0"
Gate Input
Gate Output
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Transient Response
?
The delay is essentially what determines
the clock speed of the processor
tpHL
tpLH
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Combinational vs. Sequential Logic
Combinational
Sequential
Output
(
)
f
In, Previous In
Output
(
)
f
In
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Static Complementary CMOS
VDD
In1
PMOS only
In2
PUN

InN
F(In1,In2,InN)
In1
In2
PDN

NMOS only
InN
PUN and PDN are dual logic networks
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
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PMOS Transistors in Series/Parallel Connection
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Example Gate NAND
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Example Gate NOR
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Typical sequential logic circuits
NOR-based set-reset
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Cross-Coupled NAND
Added clock
Cross-coupled NANDs
This is not used in datapaths any more,but is a
basic building memory cell
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Pipelining
Pipelined
Reference
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Full-Adder
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The Binary Adder
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The Ripple-Carry Adder
Worst case delay linear with the number of bits
td O(N)
tadder (N-1)tcarry tsum
Goal Make the fastest possible carry path circuit
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Complimentary Static CMOS Full Adder
28 Transistors
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Implementation Choices
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The Custom Approach
Intel 4004
Courtesy Intel
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Transition to Automation and Regular Structures
Courtesy Intel
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Design Metrics

• How to evaluate performance of a digital circuit
  (gate, block, )?
• Cost
• Reliability
• Scalability
• Speed (delay, operating frequency)
• Power dissipation
• Energy to perform a function

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Digital, Analog VLSI and CAD/EDA

• The introduction is mainly on digital VLSI
  circuits
• Three major challenges power dissipation,
  current leakage and process variation
• While having some similarity, analog VLSI design
  is very different from digital counterpart (up to
  10,000 transistors)
• CAD (computer aided-design) / EDA (electronic
  design automation) is the key to large scale
  complex design

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Technology Evolution (2000 data)
International Technology Roadmap for
Semiconductors
Node years 2007/65nm, 2010/45nm, 2013/33nm,
2016/23nm
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VLSI Design FFT Butterfly

• Widely used in signal processing
• Design Butterfly Unit for 2-point FFT
• Components include multiplier, adder, subtractor,
  and data management

8-point FFT composed of 12 butterflies Image from
www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/
transform/fft.html
Spencer Strunic and Matt Webb
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VLSI DesignFFTButterflyLayout
Spencer Strunic and Matt Webb
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VLSI Design 8-bit CPU

• Registers
• Store data
• Manipulate data
• ALU
• Select between many different operations to
  output
• Adder
• Adds two 8-bit numbers
• Multiplier
• Multiplies two 8-bit numbers

Brian Linder and Matt Leines
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VLSI Design8-bit CPULayout
Brian Linder and Matt Leines