A Roadmap and Vision for Physical Design ISPD-2002 April 9, 2002 Andrew B. Kahng, UCSD CSE

1
A Roadmap and Vision for Physical
DesignISPD-2002April 9, 2002Andrew B.
Kahng, UCSD CSE ECE Departmentsemail
abk_at_ucsd.eduURL http//vlsicad.ucsd.edu
2
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Coopetition
• Shared red bricks
• What we need to do, II
• A top-10 list

3
The Red Brick Wall - 2001 vs. 1999
Source Semiconductor International -
http//www.e-insite.net/semiconductor/index.asp?la
youtarticlearticleIdCA187876
4
Roadmap Acceleration and Deceleration
2001 versus 1999
Year of Production 1999 2002 2005
2008 2011 2014 DRAM Half-Pitch nm
180 130 100 70 50
35 Overlay Accuracy nm 65 45
35 25 20 15 MPU Gate Length nm 140
85-90 65 45 30-32 20-22 CD Control
nm 14 9 6 4 3 2 TOX
(equivalent) nm 1.9-2.5 1.5-1.9 1.0-1.5
0.8-1.2 0.6-0.8 0.5-0.6 Junction
Depth nm 42-70 25-43 20-33
16-26 11-19 8-13 Metal Cladding nm
17 13 10
000 Inter-Metal
Dielectric K 3.5-4.0
2.7-3.5 1.6-2.2
1.5

Source A. Allan, Intel
5
An ITRS Analogy

• ITRS is like a car
• Before, two drivers (husband MPU, wife DRAM)
• The drivers looked mostly in the rear-view mirror
  (destination Moores Law)
• Many passengers in the car (ASIC, SOC, Analog,
  Mobile, Low-Power, Networking/Wireless, )
  wanted to go different places
• This year
• Some passengers became drivers
• All drivers explain more clearly where they are
  going
• See the new System Drivers Chapter of the ITRS

6
 
HP / LOP / LSTP Device Roadmaps
   
7
Silicon Complexity Challenges

• Impact of process scaling, new materials, new
  device/interconnect architectures
• Non-ideal scaling (leakage, power management,
  circuit/device innovation, current delivery)
• Coupled high-frequency devices and interconnects
  (signal integrity analysis and management)
• Manufacturing variability (library
  characterization, analog and digital circuit
  performance, error-tolerant design, layout
  reusability, static performance verification
  methodology/tools)
• Scaling of global interconnect performance
  (communication, synchronization)
• Decreased reliability (SEU, gate insulator
  tunneling and breakdown, joule heating and
  electromigration)
• Complexity of manufacturing handoff (reticle
  enhancement and mask writing/inspection flow,
  manufacturing NRE cost)

8
System Complexity Challenges

• Exponentially increasing transistor counts, with
  increased diversity (mixed-signal SOC, )
• Reuse (hierarchical design support, heterogeneous
  SOC integration, reuse of verification/test/IP)
• Verification and test (specification capture,
  design for verifiability, verification reuse,
  system-level and software verification, AMS
  self-test, noise-delay fault tests, test reuse)
• Cost-driven design optimization (manufacturing
  cost modeling and analysis, quality metrics,
  die-package co-optimization, )
• Embedded software design (platform-based system
  design methodologies, software verification/analys
  is, codesign w/HW)
• Reliable implementation platforms (predictable
  chip implementation onto multiple fabrics,
  higher-level handoff)
• Design process management (team size / geog
  distribution, data mgmt, collaborative design,
  process improvement)

9
Big-Picture Design Technology Crises
Incremental Cost Per Transistor
Test
Manufacturing
Manufacturing
Where is the Physical Design?
SW Design
NRE Cost
Turnaround Time
Verification
HW Design

• 2-3X more verification engineers than designers
  on microprocessor teams
• Software 80 of system development cost (and
  Analog design hasnt scaled)
• Design NRE gt 10s of M ?? manufacturing NRE 1M
• Design TAT months or years ?? manufacturing TAT
  weeks
• Without DFT, test cost per transistor grows
  exponentially relative to mfg cost

10
SRC Grand Challenges

• 1. Extend CMOS to its ultimate limit
• 2. Support continuation of Moore's Law by
  providing a knowledge base for CMOS replacement
  devices
• 3. Enable Wireless/Telecomm systems by addressing
  technical barriers in design, test, process,
  device and packaging technologies
• 4. Create mixed-domain transistor and device
  interconnection technologies, architectures, and
  tools for future microsystems that mitigate the
  limitations projected by ITRS
• 5. Search for radical, cost effective post NGL
  patterning options
• 6. Provide low-cost environmentally benign IC
  processes
• 7. Increase factory capital utilization
  efficiency through operational modeling
• 8. Provide design tools and techniques which
  enhance design productivity and reduce cost for
  correct, manufacturable and testable SOC's and
  SOP's
• 9. Enable low power and low voltage solutions for
  mobile/battery conserving applications through
  system and circuit design, test and packaging
  approaches.
• 10. Enable very low cost components
• 11. Provide tools enabling rapid implementation
  of new system architectures

Where is the Physical Design?
11
SRC ICSS Key Technologies (Top 12)

• Systems
• S3.2 Early Design Space Exploration
• S1.2 Low Power, Real-Time Algorithms and
  Architectures
• S4.1 On-Chip Communication
• S1.3 High Bandwidth and/or Low Power
  Communication
• S2.4 Deep Submicron Aware Microarchitectures,
  Accounting for Noise, Power, Timing,
  Interconnects, etc.
• S1.1 High Level Specifications of Complex Systems

• Circuits
• C1.2 Digital Low Power and/or Low Voltage
  Circuit Design
• C2.1 Mixed Signal Circuits on Advanced
  Technologies
• C2.4 Mixed Signal Low Power and/or Low Voltage
  Circuit Design
• C1.1 Digital Circuits on Advanced Technologies
• C2.3 Mixed Signal Design for Test
• C2.2 Mixed Signal Noise Immune and/or Tolerant
  Circuits

Where is the Physical Design?
12
ITRS Logical/Physical/Circuit Challenges

• Efficient and predictable implementation
• Scalable, incremental analyses and optimizations
• Unified implementation/interconnect planning and
  estimation/prediction
• Synchronization and global signaling
• Heterogeneous system composition
• Links to verification and test
• Reliable, predictable fabric- and
  application-specific silicon implementation
  platforms
• Cost-driven implementation flows
• Variability and design-manufacturing interface
• Uncertainty of fundamental chip parameters
  (timing, skew, matching) due to manufacturing and
  dynamic variability sources
• Process modeling and characterization
• Cost-effective circuit, layout and reticle
  enhancement to manage manufacturing variability
• Increasing atomic-scale variability effects

13
ITRS Logical/Physical/Circuit Challenges

• Silicon complexity, non-ideal device scaling and
  power management
• Leakage and power management
• Reliability and fault tolerance
• Analysis complexity and consistent analyses /
  synthesis objectives
• Recapture of reliability lost in manufacturing
  test
• Circuit design to fully exploit device technology
  innovation
• Support for new circuit families that address
  power and performance challenges
• Implementation tools for SOI
• Analog synthesis
• Increasing atomic-scale effects
• Adaptive and self-repairing circuits
• Low-power sensing and sensor interface circuits
  micro-optical devices

14
SRC CADT PD Research Needs (2002 Draft)

• Placement and Routing
• Synthesis/Layout Integration
• Power Distribution and Analysis
• High Level Planning and Estimation
• Clocking Design and Analysis Above 15GHz
• Interconnect Synthesis and Analysis
• Timing Analysis and Verification
• Correct by Construction

Where are the ITRS challenges?
15
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Coopetition
• Shared red bricks
• What we need to do, II
• A top-10 list

16
Our Resources

• 6000 EDA RD, worldwide (Gartner/Dataquest)
• EDA tools revenue per designer has increased by
  3.9 per year over past decade
• Ratio of design value over design effort is
  perceived to decrease as level of abstraction
  moves downward from behavior to layout
• PD is at most one-sixth (by market size, or by
  headcount) of EDA and design technology
• 150-200 ISPD attendees, 60 DAC/ICCAD/ISPD papers
  in PD domain, per year

17
Research Funding Gap Study

• C. Nuese, SRC
• Research needs
• Time frame 2008 (50-, 35-, and 22-nm nodes in
  ITRS)
• Assessed by SRC Science Area Directors (131 total
  tasks)
• Research funding
• 2001 used for all data
• U.S., Europe, Japan and Asia-Pacific
• Assumed of RD (or of Sales)

Source C. Nuese / SRC
18
Funding Model
Source C. Nuese / SRC
19
Research Funding Gap Results
Science Area Tasks Funds ( M)
Front-end Processing 22 150
Proc Integr, Dev Struct 15 280
Patterning 25 245
Interconnects 13 153
Design CAD 26 280
Ckt Des Sys Arch 20 168
ESH 5 30
Factory Integr 5 100

M M
RESEARCH NEEDS
Total Science Areas
RESEARCH FUNDING
Industry
Semiconductor Mfg 413
Equipment Suppliers 22
Materials Suppliers 3
EDA Suppliers 4
Total Industry
Government
U.S. 254
Europe 198
Japan Asia-Pac 96
Total Government
Total Research Funding
WW RESEARCH GAP
Industry Sales (B) RD (B) LT ITRS (M)
Semiconductors 170 21 413
Equip Suppliers 35 4 22
Matrl Suppliers 26 1 3
EDA Suppliers 4 1 4
Total
Science Area Tasks Funds (M)
Front-end Processing 22 150
Proc Integr, Dev Struct 15 280
Patterning 25 245
Interconnects 13 153
Design CAD 26 280
Ckt Des Sys Arch 20 168
ESH 5 30
Factory Integr 5 100

Agency/Program LT ITRS Funds (M)
DARPA
Microsystems Tech Office 88
Info Tech Office 18
Defense Sciences Office 3
DUSD (ST)
Misc 10
Nanotechnology 45
Microelectronics 6
DoE
Misc 30
NSF
Electronics 1
Comp Info Sciences 5
Engr Res Centers 8
Nanotechnology 41
Totals
Industry Sales (B) RD (B) LT ITRS (M)
Semiconductors 170 21 413
Equip Suppliers 35 4 22
Matrl Suppliers 26 1 3
EDA Suppliers 4 1 4
Total
Program Amount (M)
European Community 6th Framework 95
MEDEA-Plus 23
IMEC, LETI, Fraunhofer 55
Other 25
Total 198
Program Amount (M)
Sub-0.1 micron Project 30
STARC (next phase) 21
SELETE (next phase) 31
MARAI 14
Total 96
Agency/Program LT ITRS Funds (M)
DARPA
Microsystems Tech Office 88
Info Tech Office 18
Defense Sciences Office 3
DUSD (ST)
Misc 10
Nanotechnology 45
Microelectronics 6
DoE
Misc 30
NSF
Electronics 1
Comp Info Sciences 5
Engr Res Centers 8
Nanotechnology 41
Totals
Foreign redundancy and inaccessibility
significantly increase size of effective research
gap.
Source C. Nuese / SRC
20
Anatomy of ITRS PD Needs

• Analog layout synthesis and reuse
• Layout-BIST synergies for UDSM fault models
• New paradigms for global signaling,
  synchronization and system-level interconnect
• Modeling and simulation
• Mitigation of increased process variability and
  non-recurring costs in mask and foundry flows
• Multi-(Vdd, Vt, tox, biasing) performance
  optimization

21
Anatomy of Recent PD Literature

• (1) placement / partitioning
• (2) routing / global routing / wireplanning
• (3) interconnect tree (buffered / Steiner / RAT /
  ) construction
• (4) floorplanning / block packing / macro-cell
  placement
• (5) performance optimization (sizing, etc.)
• (6) RTL-down methodology / flow
• (7) clock
• (8) power
• (9) custom layout (transistor-level / migration /
  compaction)
• (10) analog
• (11) manufacturability / yield
• (12) logical-physical interactions
• (13) signal integrity
• Table DAC (Y) / ICCAD (Y) / ISPD (Y1), in Y
  1996, , 2001

22
Distribution of Physical Design Papers Among 13
Topics
Where are the ITRS challenges?
23
Dissimilarity by Compression ?
File .gz 97.gz 02.gz 97 02
ABK 665 2008 1985 0.937 0.939
CADT 187 1525 1498 0.934 0.933
ICSS 352 1685 1660 0.930 0.931
L/P/C 793 2118 2066 0.925 0.906
Si/Sys 814 2143 2104 0.927 0.918
Strat 620 1941 1911 0.922 0.919

• ((ISPD97 CADT).gz CADT.gz) / ISPD97.gz
• ((ISPD97 ISPD02).gz ISPD02.gz) / ISPD97.gz
  0.78

24
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Coopetition
• Shared red bricks
• What we need to do, II
• A top-10 list

25
What Is Going On Here?

• Three pernicious phenomena
• (1) Long lead times and latencies formulation
  to solution to technology transfer to marketplace
  
• (2) High startup costs and other barriers to
  entry in research
• (3) Research field recreates itself in its own
  image

26
Its Not A Moving Target

• PD roadmap has been static
• Convergent integration of logic, timing, spatial
  embedding
• Unification of incremental timing/SI closure with
  PA backplane
• Methodology and routing contexts
• Some references
• NTRS/ITRS since 1994
• 1995 Sematech CHDS specification
• L. Scheffer, PDW96 Were Solving the Wrong
  Problems
• Other examples listed in paper

27
Hello?
28
Hello??
29
Too Much Back-Filling?

• Practice of putting well-known and already
  commercialized techniques into the public
  literature
• Some impact on IP and research efficiency, but
  only if there is adequate transfer of the
  resulting technology!
• Standard planning framework, next-generation
  detailed routers, etc. are better left to
  industry
• Academia would benefit from more
  industry-strength shared research infrastructures

30
What Should Be Novel in Research?

• Novelty in formulation, or novelty in
  optimization?
• Claim PD is focusing more on novel problem
  statements, while only transferring or reusing
  core optimization techniques
• 15 years ago PD was the source of simulated
  annealing, LP relaxation/rounding, hierarchical
  routing, etc.
• Past decade mostly transferring methods (e.g.,
  multilevel (PDW96, DAC97))
• Again Were solving the wrong problems
• Cf. packing obsession in floorplanning
  literature
• Shortage of optimization tools
• No shortage of problems

31
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Mindset Change 1 Coopetition
• Mindset Change 2 Shared red bricks
• What we need to do, II
• A top-10 list

32
Vision Improved Design Technology Productivity

• MARCO GSRC Calibrating Achievable Design theme
• http//vlsicad.ucsd.edu/GSRC/
• Improved design technology planning (specify)
  
• What will the design problem look like? What do
  we need to solve?
• Improved execution (develop)
• How can we quickly (TTM) develop the right design
  technology (QOR)?
• Reusable, commodity, foundation CAD-IP ( new
  publication standards)
• Improved measurement (measure and improve )
• Did we solve the problem (QOR)? Did the design
  process improve? Did we increase the envelope of
  achievable design?
• Design tool/process metrics, design process
  instrumentation and continuous process
  improvement
• Ethos of coopetition (cooperation among
  competitors)

33
Living ITRS Framework
34
CAD-IP Reuse

• Rapid development and evaluation of fundamental
  algorithm technology, via CAD-IP reuse
• CAD-IP Data models and benchmarks
• context descriptions and use models
• testcases and good solutions
• CAD-IP Algorithms and algorithm analyses
• mathematical formulations
• comparison and evaluation methodologies for
  algorithms
• executables and source code of implementations
• leading-edge performance results
• CAD-IP Traditional (paper-based) publications

35
MARCO GSRC Bookshelf A Repository for CAD-IP

• New element of VLSI CAD culture
• Community memory currently centered in back-end
• data models, algorithms, implementations
• repository for open-source foundation CAD-IP
• Publication medium that supports efficient CAD
  RD
• benchmarks, performance results
• algorithm descriptions and analyses
• quality implementations (e.g., open-source UCLA
  PDTools)
• Enables comparisons to identify best approaches
• Enables communication by industry of use models,
  problem formulations
• http//gigascale.org/bookshelf/
• Have you open-sourced your code in the Bookshelf?

36
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Mindset Change 1 Coopetition
• Mindset Change 2 Shared red bricks
• What we need to do, II
• A top-10 list

37
What Is A Red Brick ?

• Red Brick ITRS Technology Requirement with no
  known solution
• Alternate definition Red Brick something
  that REQUIRES billions of dollars in RD
  investment

38
Another ITRS Analogy

• ITRS technologies are like parts of the car
• Every one takes the engine point of view when
  it defines its requirements
• Why, you may take the most gallant sailor, the
  most intrepid airman, the most audacious soldier,
  put them at a table together what do you get?
  The sum of their fears. - Winston Churchill
• All parts must work together to make the car go
  smoothly
• Need global optimization of resource allocations
  with respect to requirements ? shared red bricks

39
Design-Manufacturing Integration

• 2001 ITRS Design Chapter Manufacturing
  Integration one of five Cross-Cutting
  Challenges
• Goal share red bricks with other ITRS
  technologies
• Lithography CD variability requirement ? new
  Design techniques that can better handle
  variability
• Mask data volume requirement ? solved by
  Design-Mfg interfaces and flows that pass
  functional requirements, verification knowledge
  to mask writing and inspection
• ATE cost and speed red bricks ? solved by DFT,
  BIST/BOST techniques for high-speed I/O, signal
  integrity, analog/MS
• Does X initiative have as much impact as copper?

40
Example Red Brick Dielectric Permittivity
Do we really need this?
Bulk and effective dielectric constants Porous
low-k requires alternative planarization
solutions Cu at all nodes - conformal barriers
C. Case, BOC Edwards ITRS-2001
41
Example Red Brick Copper Resistivity
Is this even possible?
Conductor resistivity increases expected to
appear around 100 nm linewidth - will impact
intermediate wiring first - 2006
Courtesy of SEMATECH
C. Case, BOC Edwards ITRS-2001
42
PD PIDS (Devices/Structures)

• CV/I trend (17 per year improvement)
  constraint
• Huge increase in subthreshold Ioff
• Room temperature increases from 0.01 uA/um in
  2001 to 10 uA/um at end of ITRS (22nm node)
• At operating temperatures (100 125 deg C),
  increase by 15 - 40x
• Standby power challenge
• Manage multi-Vt, multi-Vdd, multi-Tox in same
  core
• Aggressive substrate biasing
• Constant-throughput power minimization
• Modeling and controls passed to operating system
  and applications
• Aggressive reduction of Tox
• Physical Tox thickness lt 1.4nm (down to 1.0nm)
  starting in 2001, even if high-k gate dielectrics
  arrive in 2004
• Variability challenge 10 lt one atomic
  monolayer

43
PD Lithography

• 10 CD uniformity is a red brick today
• 10 lt 1 atomic monolayer at end of ITRS
• This year Lithography, PIDS, FEP agreed to
  raise CD uniformity requirement to 15 (but
  still a red brick)
• Design for variability
• Novel circuit topologies
• Circuit optimization (conflict between slack
  minimization and guardbanding of quadratically
  increasing delay sensitivity)
• Centering and design for /wafer
• Design for when devices, interconnects no longer
  100 guaranteed correct?
• Potentially huge savings in manufacturing,
  verification, test costs

44
PD Assembly and Packaging

• Goal cost control (0.07/pin, 2 package, )
• Grand Challenge for AP work with Design to
  develop die-package co-analysis, co-optimization
  tools
• Bump/pad counts scale with chip area only
• Effective bump pitch roughly constant at 300um
• MPU pad counts flat from 2001-2005, but chip
  current draw increases 64
• IR drop control challenge
• Metal requirements explode with Ichip and wiring
  resistance
• Power challenge
• 50 W/cm2 limit for forced-air cooling MPU area
  becomes flat because power budget is flat
• More control (e.g., dynamic frequency and supply
  scaling) given to OS and application
• Long-term Peltier-type thermoelectric cooling,

45
PD Manufacturing Test

• High-speed interfaces (networking, memory I/O)
• Frequencies on same scale as overall tester
  timing accuracy
• Heterogeneous SOC design
• Test reuse
• Integration of distinct test technologies within
  single device
• Analog/mixed-signal test
• Reliability screens failing
• Burn-in screening not practical with lower Vdd,
  higher power budgets ? overkill impact on yield
• Design challenges DFT, BIST ? PD IS in the
  loop!
• Analog/mixed-signal
• Signal integrity and advanced fault models
• BIST for single-event upsets (in logic as well as
  memory)
• Reliability-related fault tolerance

46
How to Share Red Bricks

• Cost is the biggest missing link within the ITRS
• Manufacturing cost (silicon cost per transistor)
• Manufacturing NRE cost (mask, probe card, )
• Design NRE cost (engineers, tools, integration,
  )
• Test cost
• Technology development cost ? who should solve a
  given red brick wall?
• Return On Investment (ROI) Value / Cost
• Value needs to be defined (design quality,
  time-to-market)
• Understanding cost and ROI allows sensible
  sharing of red bricks across industries
• PD is at the heart of these potential
  partnerships
• PD is in the best position to share RD
  investment!

47
Outline

• What we need
• ITRS challenges, logical/circuit/physical needs
• SRC needs
• What we do
• Allocation of effort, versus needs and resources
• Harmful practices
• What we need to do
• Coopetition
• Shared red bricks
• What we need to do, II
• A top-10 list

48
A Top-10 List

• (0) Sensible unifications to co-optimize global
  signaling, manufacturability enhancement, and
  clock/test/power distribution
• (1) Fundamental new combinatorial optimization
  technologies (and possibly geometry engines) for
  future constraint-dominated layout regimes
• (2) New decomposition schemes for physical design
• (3) Global routing that is truly path-timing
  aware, truly combinatorial, and able to invoke
  atomistic interconnect synthesis
• (4) In-context layout synthesis that maximizes
  process window while meeting electrical
  (functional) spec

49
A Top-10 List

• (5) Efficient analog and mixed-signal layout
  synthesis
• (6) Methods for synchronization and global
  signaling at multi-GHz or Gbps, extending to
  system-level
• (7) Analysis, modeling and simulation methods
  that are tied more closely to PD syntheses, and
  that adapt to resource and accuracy and fidelity
  constraints
• (8) Revival of platform-specific (parallel,
  distributed, hardware-accelerated) algorithm
  implementations
• (9) Mindset changes, including a culture of
  duplicating, deconstructing and debunking

50
Conclusions

• PD roadmap is static and well-known
• There is a mismatch with semiconductor industry
  needs, and basic problems remain untouched
• We in academia should not overemphasize
  back-filling and formulation over innovation and
  optimization
• As a community, we must become more mature and
  efficient in how we prioritize research
  directions and use our human resources
• The scope of PD must expand up, down, out, back
  even as renewed focus is placed on basic
  optimization technology
• PD is at the heart of shared red bricks we
  should and must seize this opportunity for new
  RD investment

51
Thank you !
52
Analogy 1

• ITRS is like a car
• Before, two drivers (husband MPU, wife DRAM)
• The drivers looked mostly in the rear-view mirror
  (destination Moores Law)
• Many passengers in the car (ASIC, SOC, Analog,
  Mobile, Low-Power, Networking/Wireless, )
  wanted to go different places
• This year
• Some passengers became drivers
• All drivers explain more clearly where they are
  going

53
Design Chapter Outline

• Introduction
• Scope of design technology
• Complexities (silicon, system)
• Design Cross-Cutting Challenges
• Productivity
• Power
• Manufacturing Integration
• Interference
• Error-Tolerance
• Details given w.r.t. five traditional technology
  areas
• Design Process, System-Level, Logical/Physical/Cir
  cuit, Functional Verification, Test
• Each area table of challenges mapping to
  driver classes

54
2001 Big Picture

• Message Cost of Design threatens continuation
  of the semiconductor roadmap
• New Design cost model
• Challenges are now Crises
• Strengthen bridge between semiconductors and
  applications, software, architectures
• Frequency and bits are not the same as efficiency
  and utility
• New System Drivers chapter, with productivity and
  power foci
• Strengthen bridges between ITRS technologies
• Are there synergies that share red bricks more
  cost-effectively than independent technological
  advances?
• Manufacturing Integration cross-cutting
  challenge
• Living ITRS framework to promote consistency
  validation

55
Design Cost Model

• Engineer cost per year increases 5 / year
  (181,568 in 1990)
• EDA tool cost per year (per engineer) increases
  3.9 per year (99,301 in 1990)
• Productivity due to 8 major Design Technology
  innovations (3.5 of which are still unavailable)
  RTL methodology In-house PR Tall-thin
  engineer Small-block reuse Large-block reuse
  IC implementation suite Intelligent testbench
  Electronic System-level methodology
• Matched up against SOC-LP PDA content
• SOC-LP PDA design cost 15M in 2001
• Would have been 342M without EDA innovations and
  the resulting improvements in design productivity

56
Design Cost of SOC-LP PDA Driver
57
Methodology Basic Precepts

• Exploit reuse
• Evolve rapidly
• Analyses and simulation ? models and
  verifications ? objectives and constraints for
  synthesis and optimization
• Bottom-up commoditization (e.g., analyses,
  physical layout / verification)
• Avoid iteration
• Replace verification by prevention
• Improve predictability
• Orthogonalize concerns
• Behavior from architecture timing from layout
  
• Expand scope, and unify
• E.g., down to manufacturing, up to package/system

58
Future Design System Architecture
59
Analogy 2

• ITRS technologies are like parts of the car
• Every one takes the engine point of view when
  it defines its requirements
• Why, you may take the most gallant sailor, the
  most intrepid airman, the most audacious soldier,
  put them at a table together what do you get?
  The sum of their fears. - Winston Churchill
• All parts must work together to make the car go
  smoothly
• (Design Steering wheel and/or tires but has
  never squeaked loudly enough)
• Need global optimization of requirements

60
FO4 INV Delays Per Clock Period

• FO4 INV inverter driving 4 identical inverters
  (no interconnect)
• Half of freq improvement has been from reduced
  logic stages

61
Source 2001 ITRS - Exec. Summary, ORTC Figure
62
Source 2001 ITRS - Exec. Summary, ORTC Figure
63
Source A. Allan, Intel
64
Roadmap Changes Since 2000

• Next node 0.7x half-pitch or minimum feature
  size
• ? 2x transistors on the same size die
• 90nm node in 2004 (100nm in 2003)
• 90nm node ? physical gate length 45nm
• MPU/ASIC half-pitch DRAM half-pitch in 2004
• Previous ITRS (2000) convergence in 2015
• Psychology everyone must beat the Roadmap
• Reasons density, cost reduction, competitive
  position
• TSMC CL010G logic/mixed-signal SOC process risk
  production in 4Q02 with multi-Vt, multi-oxide,
  embedded DRAM and flash, low standby power
  derivatives,

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Problem Statements V

• Pass functional intent down to OPC insertion
• OPC insertion is for predictable circuit
  performance, function
• Problem make only corrections that win ,
  reduce perf variation (i.e., link to performance
  analysis, optimizations and sensitivities)
• Pass limits of mask verification up to layout
• Problem avoid making corrections that cant be
  manufactured or verified
• // I.e., 2-way fat pipe between process and
  design !
• SPICE models are not a sufficient process
  abstraction

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Problem Statements VI

• Minimize data volume
• Problem make corrections that win , reduce
  perf variation up to some limit of data volume
  for resulting layout ( mask complexity, cost)
• Layout needs models of OPC insertion process
• Problem taxonomize implications of layout
  geometry on cost of the OPC that is required to
  yield function or faithfully print the geometry
• find a realistic cost model for breaking
  hierarchy (including verification,
  characterization costs)

67
Other Oldies But Goodies

• Constraint-dominated and cost-driven layout
• Good practices (no doglegs, no Ts, even
  fingering)
• Constrained orientations (no 45s, one direction
  only)
• Constrained pitches (forbidden gap rules)
• Halation (width-dependent spacing) rules
• Electrically correct, manufacturing cost-aware
  detailed routing
• Auto-PR productivity
• Guaranteed composability is foundation of
  standard-cell productivity
• Library generation must support PSM layout
  composability
• Layout on the fly (liquid library cells for
  performance, yield)

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Other Oldies But Goodies

• Sane RCX / PA flow with respect to area fill
• Area fill breaks RCX extraction
• Must be modeled / predicted at timing / signal
  integrity signoff during auto-PR
• Tradeoffs and correct models (grounded vs.
  ungrounded synergies between fill and
  printability (as opposed to planarization) must
  be understood
• PSM, OPC (?) and Fill must be owned by physical
  design, not physical verification
• PV tools have Boolean, purely geometric
  infrastructure
• PV tools report errors (e.g., phase conflict),
  but are not empowered to fix (e.g., shift/compact
  layout
• Miscellaneous
• Hierarchy, data volume, reuse concerns
• New tool integrations compaction, on-the-fly
  cell synthesis, incremental detailed routing,
  graph-based (verification-type) layout analyses,
  performance and logic optimizations

69
Cost of Manufacturing Test
Is this better solved with Automated Test
Equipment technology, or with Design (for Test,
Built-In Self-Test) ? Is this even solvable with
ATE technology alone?