Engineering

1
Electronic System Design GroupDAQ Projects

• Group Meeting
• CR13/R68
• 29th August 2005
• 1000-1200

2
Generic DAQ

• New Batch x30 Off
• 28 Back Ends passed JTAG
• 2 Back Ends failed JTAG
• Assembly Problem with FE SCSI
• Problem modules returned to Manufacturer
• New order from Richard Farrow
• x4 Off
• Meet from 5 spares in the new Batch

3
CALICE

• Final Batch of 7 Off for DESY in progress
• September-October
• Rob Halsall (PM)
• Adam Baird

4
MEDG - MI3 MAPS

• Michelle working on common firmware design
• RAM based Sequencer for control of Sensor ASICs
• Application to multiple chips
• OPIC

5
MEDG - CIQE

• Quantum Computing
• Control readout under Matlab
• Ed Freeman
• See Forum talk

6
DIAMOND - PENELOPE
CHIP
x8 Off
CHIP
96mm
1v5
2v5
CHIP
328MB/S
PWR
CHIP
JTAG
51mm
SDRAM 64MByte
SDRAM 64MByte
CHIP
SFP Opto Transceiver
FPGA
80MB/s
CHIP
3v3
SFP Opto Transceiver
CHIP
80MB/s
328MB/S
SDRAM 64MByte
SDRAM 64MByte
CHIP
FLASH
CPLD
CHIP
XTL1
2v5 RF
3v3
XTL2
CHIP
CHIP

• Postponed!
• Possibly replaced by DIFFEX

CHIP
7
PETTRA
CFD 1
CFD 2
CFD 3
CFD 4
Opto DAQ Engine
ADC 1
ADC 2
ECL tx
ECL rx
Slow DACs
Fast DACs

• Test bench work
• About to start design capture in DO

8
Opto DAQ

• CFI BID III - 100K
• Moving back toward firmware software
  development with development boards
• Project Spec re-write...
• Objectives
• Improve protocol efficiency
• Software
• New results (preliminary)
• 1G PC-PC 68 MB/s
• 10G PC-PC 112MB/s

9
CFI - FPGA Computing

• Re - Bid partially succesful - 50K awarded
• Demonstrate an Algorithm running in an FPGA
• Double precision floating point cores available
  in coregen
• Use a virtex 4 dev board
• Collaborate with CSED at DL
• Simulation/COTS Hardware
• Use info to refine FPGA Computing Facility
  Development Bid for October
• ISIS, SR, LASER EID, CSED, E-Science...

10
Internal RD - Network Core

• Choices
• 3rd party H/W IP
• EDKRTOSEMAC
• ESDG H/W IP EMAC
• Investigate
• 10/100/1000 10G
• EMAC UDP framer

11
Internal RD

• Asynchronous Pulse characterisation IP
• Time Energy
• CFD replacement
• ISIS, PETRRA Neutrino
• Rob John M

12
In the pipeline
13
MAPS - Laser Tweezers

• 3 Staff Months of effort for design of FPGA
  engine
• Invited to bid for more effort
• Depends on Laser Department recruitment success
• RH Interviewing candidates next week

14
MEDG - Neural MAPS
DDR SDRAM
ADC
Opto Trx
MAPS
Gbit/s
Server PCs
FPGA
ADC
Opto Trx
Gbit/s
DDR SSRAM

• 500 Mbyte/s readout logged to disk...

15
MEDG - DIFFEX

• Based on Opto DAQ engine used in CIQE
• PCB Back from manufacture
• Design a high end version for DIAMOND

16
New Opportunities
17
PPD - T2K 280m readout

• Proposal for DAQ has been presented to the
  collaboration
• Ongoing...

18
SND at DL - SMARTPET

• Telecon after meeting...

19
More MEDG Projects!