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Builtin Self Test


It is a true dual-port memory core ... STEP3: target faults in the dual-port functionality. 23. STEP1 ... Efficient Test for Realistic Faults in Dual-Port SRAMS. ... – PowerPoint PPT presentation

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Title: Builtin Self Test

Built-in Self Test
  • Panpan Hu
  • panpan.hu_at_huskers.unl.edu
  • Built-in self-test is a DFT scheme in which all
    the components of an external tester are
    essentially integrated into the chip so that
    either an external tester is eliminated or a much
    simpler one will do.

  • Overview of BIST
  • Background
  • The Economic Case
  • BIST in Logic Circuit
  • Memory BIST
  • General info
  • March test
  • A Case Study An Efficient BIST for Testing
    Virtex-4 block RAMs

  • Usually, we have assumed that testing of logic
    circuits is done by externally applying the test
    inputs and comparing the results with the
    expected behavior of the circuit. This requires
    connecting external equipment to the circuit
    under test.
  • An interesting question is whether it is possible
    to incorporate the testing capability within the
    circuit itself so that no external equipment is
  • A possible BIST arrangement

Chip boundary
Test result compressor
Test vector generator
Circuit under test
The Economic Case for BIST
  • Complexity. One unfortunate property of large
    VLSI circuits is that testing cannot be easily
    partitioned. For test development effort, BIST
    provides a way to decompose the electronic
  • Quality. Typical quality requirements are 98
    single stuck-fault coverage or 100 interconnect
    fault coverage.
  • Test Generation Problems. It is difficult to
    carry a test stimulus involving hundreds of
    chip inputs through many layers. BIST
    localizes testing, which eliminates these
  • BIST is lower test development cost, because
    BIST can be automatically added to a circuit with
    a CAD tool.

Built-in self-test cost
  • This table shows the relative BIST costs at the
    chip,board,and system levels of packaging

BIST in Logic Circuit
  • Generating the test vectors on-chip preudorandom
  • LFSRs(Linear feedback shift registers)
  • Single/multiple-input compressor circuit(SIC/MIC)
  • Built-in Logic Block Observer(BILBO)
  • Signature analysis
  • Boundary scan

  • BIST is currently used extensively in memory
    designs but not as much in logic designs.

Memory BIST
  • Embedded RAM memories are perhaps the hardest
    type of digital circuit to test, because memory
    testing requires delivery of a huge number of
    pattern stimuli to the memory and the readout of
    an enormous amount of cell information.
  • With memory design for testability (DFT), the
    most time-consuming part of a memory test
    algorithm is implemented on-chip, and reduces the
    memory test time by an order of magnitude.
  • Most memory BIST schemes exploit the parallelism
    within the memory device to achieve a massive
    reduction in test time (and therefore cost).

  • memory BIST requires an address generator (often
    an LFSR). An LFSR is better for march test BIST
    than a binary counter,because
  • it uses substantially less area and can easily be
    made self-testable.
  • the LSFR can be adjusted to provide the all-zero
    pattern and the forward and exact reverse LSFR
  • Another advantage is that the probability of an
    address bit changing is equal for all address

  • The comparator eliminates the need to generate
    the good machine response and implicitly assumes
    that only a minority of the memory array outputs
    are incorrect at any given time.

March Test
  • The march tests are appropriate for SRAM testing.

A Case Study An Efficient BIST for Testing
Configurable Embedded Memories in FPGAs
  • Using the latest Virtex 4 (V4) FPGA from Xilinx
    as model
  • At 9,936Kbits of block RAM (18K each), the V 4
    FX140 is quite possible the largest FPGA
    currently manufactured
  • It is a true dual-port memory core
  • The wider memory configurations are 512 x 36, 1K
    x 18, and 2K x 9 .

Memory BIST Architecture
  • Each half of the V4 has its own Test Pattern
    Generator (TPG) that drives the block RAMs in its
    respective half.
  • The output response analyzers (ORAs) compare the
    output from each block RAM with the output of an
    adjacent block RAM.

TPG Port Model
  • The TPG for this BIST architecture must be able
    to generate a sequence of different march tests.
    This figure illustrates the input and output
    ports of such a TPG.
  • The mode bit vector allows the user to set the
    march test to be performed.
  • The addition of dual address and data lines
    provides support for the needed dual port
  • Varying active levels should be tested during the
    many BIST cycles the TPG will generate.

Overview of March Algorithms
  • March LR 2
  • March LR with DBS3
  • MarchS
  • S2PF and D2PF1

March LR 2
  • transition faults (TF)
  • idempotent coupling faults (CFid)
  • state coupling faults (CFst)
  • disturb faults (CFdst)
  • data retention faults (DRF)
  • Therefore, this table shows that this test
    sequence is superior to March C-

March LR with DBS3
  • In 3, Goor describes a method for efficiently
    converting a bit-oriented memory march test such
    as March LR to word-oriented memory (WOM) tests.
  • WOM march tests can detect inter-word faults and
    intra-word faults.
  • V4 block RAMs have the ability to address words
    within a line of memory. In a 512 x 36
    configuration, there are four words and a parity
    bit for each word.
  • Instead of zeros and ones, Goor describes a
    sequence of bits that is called a background data
    sequence (BDS).

  • We have discussed it before.
  • The MATS memory test algorithm is the simplest
    march test to detect all AFs (address decoder
    faults) for memory resource.
  • MATS is needed to exercise the programmable
    address decoder in each of the remaining
    configurations (16k x 1).

S2PF and D2PF1
  • In 1, Goor describe a fault model for two-port
  • They define two types of faults likely to occur
    in dual-port memories Strong faults and weak
  • Strong faults are those faults which can be
    sensitized by using a single-port (SP) test such
    as those described previously.
  • Weak faults are defined as a fault partially
    sensitized during an operation. Only when
    multiple weak faults are sensitized does a fault
    become visible.
  • March s2PF- is a march test that addresses both
    ports at the same time with the same march
  • (p1 p2)
  • nno operaton
  • --any allowed operation
  • Ccolumn
  • Rrow

March s2PF
S2PF and D2PF1 Cont.
  • March d2PF uses a double-addressing scheme. Note
    that C and R in Figure 4 are the number of
    address location on each port of the block RAM.

March d2PF
Application to Virtex 4 Block Rams
  • As in all testing algorithms, the goal is to
    maximize fault coverage while minimizing the test
  • In order to test the V4 block RAMs efficiently,
    it is proposed that the testing should take place
    in three distinct phases.
  • STEP1 detect faults in the 18K memory cells.
  • STEP2 target faults in the programmable address
    decoder in each of the remaining memory modes.
  • STEP3 target faults in the dual-port

  • the March LR algorithm with BDS is used to verify
    that the RAM matrix (containing the memory cells)
    is fault-free.
  • A procedure is given in 3 for converting March
    LR to a word-oriented test by incorporat-ing BDS.
  • The two widest memory configurations (51236-bit
    and 1K18-bit) have the ability of writing
    byte-wise to the memory locations.
  • After March LR with BDS testing, the RAM matrix
    is assumed to be fault-free if the ORAs did not
    detect any mismatch during the circular
  • As a result, BDS is applied only during the first
    BIST configuration since once tested there is no
    need to repeat pattern sensitivity and coupling
    fault tests in the RAM matrix.

STEP 2 and STEP 3
  • The next test algorithm, MATS 6, is used to
    test for address decoder faults in the
    programmable address decoder.
  • MATS is the most efficient test known to detect
    all address decoder faults.
  • This helps to reduce the overall test time
    associated with the block RAMs.
  • SETP 3, dual-port testing, is achieved by using
    March s2pf- and March d2pf 1.

Performance Analysis
  • Virtex-4 block RAMs share many similarities with
    the block RAMs in Virtex 2
  • As such, a comparison of the expected performance
    should be beneficial.

Performance Analysis Cont.
  • As can be seen from Table 1 and 2 where the total
    test time, in terms of BIST clock cycles, is
    compared with that for similar block RAMs in
    Virtex 2 using the BIST approach including March
  • In that BIST approach, the March LR algorithm was
    used to test all single-port RAM modes of
  • As a result, it required about 2.5 times more
    BIST execution clock cycles compared to what we
    have currently developed for Virtex-4.

  • 1 Hamdioui, Said and van de Goor, A.J.
    Efficient Test for Realistic Faults in Dual-Port
    SRAMS. IEEE Transactions on Computers, VOL. 51.
    NO. 5, 2002
  • 2 van de Goor, A.J. et al. March LR A Test
    for Realistic Linked Faults. 14th VLSI Test
    Symposium, pp. 272-281, 1996
  • 3 van de Goor, A.J. and Tlili, I.B.S. March
    tests for word-oriented memories. Design,
    Automation and Test in Europe, 1998.,
    Proceedings, pp 501 508, . 1998
  • 4 van de Goor, A.J. Testing Semiconductor
    Memories Theory and Practice. Comtex Publishing
    Gouda, Netherlands, 1998
  • 5 Virtex-4 User Guide, UG070 (v1.4), Xilinx,
    Inc., 2005, available at www.xilinx.com
  • 6 C. Stroud, A Designers Guide to Built-In
    Self-Test, Kluwer Academic Publishers, Boston,
  • 7 Virtex 1 Data Sheet, DS112 (v1.5), Xilinx,
    Inc., 2001, available at www.xilinx.com
  • 8 C. Stroud and S. Garimella, BIST and
    Diagnosis of Multiple Embedded Cores in SoCs,
    Proc. Intl Conf. on Embedded Systems
    Applications, pp. 130-136, 2005

Thank you
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