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PPT – BuiltIn SelfTest Design for an Arithmetic Calculation Logic using LFSRs PowerPoint presentation | free to view - id: 28ca2-MDI2Y

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Built-In Self-Test Design for an Arithmetic

Calculation Logic using LFSRs

- Presented by
- Group 2
- Fariborz Fereydouni ( 4762894 )

Donglin Li ( 4857372 )

Contents

- 1. Introduction
- 2. BIST Related Technologies
- 3. BIST Design of the Calculation Logic
- 4. Design Implementation Verification
- 5. Conclusion

Background

- Goal of this project
- --- Offering high reliability for the

Circuit Under Test (CUT) A Calculation Logic - Design For Testability (DFT)
- --- the goal is to increase the ease

with which a device can be tested - DFT Focus

- --- Two 16-bit adders
- DFT technique adopted
- --- Built-In Self-Test

Why BIST

- Approaches to Design for Testability
- Ad Hoc (Problem oriented)Partitioning, Test

points - Structured Scan Design, Boundary scan
- BIST
- Advantages of BIST
- Efficiently reduce test cost
- At-speed test
- Anytime-anywhere testing
- Easy diagnostics

Contents

- 1. Introduction
- 2. BIST Related Technologies
- 3. BIST Design of the Calculation Logic
- 4. Design Implementation Verification
- 5. Conclusion

Definition and principles of BIST

- BIST the capability of a chip, board, or system

to test itself - The goal of BIST is to add devices to a design

that will allow it to test itself - Three parts to form BIST
- Test Pattern Generator (TPG)
- Output Response Analyzer (ORA)
- Test Controller

- TPG - Pseudo Random Pattern Generator implemented

with a Linear Feedback Shift Register (LFSR) - ORA - Signature Analyzer implemented with a LFSR
- LFSR Simple architecture, easy to implement

Architecture of LFSR

- Typical parts of LFSR
- D-flip-flops --- to form shift register
- XOR Gates --- to form feedback logic

Applications of LFSR for BIST

- Maximal length LFSR as Pseudo Random Pattern

Generator (TPG) - Maximal length --- 2n-1 states
- Output sequences have the character of Pseudo

Random

Internal-XOR Architecture of LFSR

External-XOR Architecture of LFSR

Applications of LFSR for BIST (Cont.)

- Maximal length LFSR as Signature Analyzer (ORA)
- Different input sequences correspond to different

output sequences

Fault Models

- Typical fault models
- Stuck-at fault model
- Stuck-open fault model
- Bridging fault model
- Delay fault model
- Fault models adopted
- Single stuck-at fault model (90, map)

Contents

- 1. Introduction
- 2. BIST Related Technologies
- 3. BIST Design of the Calculation Logic
- 4. Design Implementation Verification
- 5. Conclusion

Circuit Under Test

Circuit Under Test

- Our test is focused on the 16-bit adder, which is

built by cascading four 4-bit Carry Look-ahead

Adders (CLAs).

Carry Look-ahead Adder

- Boolean Equations
- Pi Ai ? Bi Carry propagate
- Gi AiBi Carry generate
- Si Pi ? Ci Sum
- Ci1 Gi PiCi Carry Out
- Let's apply these equations for a 4-bit adder
- C1 G0 P0C0
- C2 G1 P1C1 G1 P1G0 P1P0C0
- C3 G2 P2C2 G2 P2G1 P2P1G0 P2P1P0C0
- C4 G3 P3C3 G3 P3G2 P3P2G1 P3P2P1G0

P3P2P1P0C0

Carry Look-ahead Adder

Carry Look-ahead Adder

BIST design of the 16-bit adder

- Test pattern Generation
- TPG of 4-bit CLA
- TPG of the 16-bit adder
- Output response Analysis
- MISR
- Comparing construct

Test pattern generation of 4-bit CLA

- Single stuck-at faults of a 4-bit CLA can be

covered by the following test patterns

81 / 512 16

Test pattern generation of the 16-bit adder

- The 9-bit test patterns for the 4-bit CLA can be

extended to 33-bit test patterns for the 16-bit

adder in a way that each time one of the four

4-bit CLAs will be tested independently. - The whole 16-bit adder will be tested one by one

in four steps and each step takes 81 test clock

cycles respectively. - Take the second step, the test for the second

4-bit CLA from the Least Significant Bit of the

adder, for example the test pattern for this

step will be like - a, b, cin
- (0000 0000 a_t cin_t cin_t cin_t

cin_t ) (0000 0000 b_t 0000)

cin_t, - where a_t, b_t, cin_t is the test pattern for

the 4-bit CLA. - Note that the carry chains between these three

CLAs are also tested at the same time

Test pattern generation of the 16-bit adder

- Comparison between the exhaustive test and our

improved test

- A very big reduction of the test set !

Output Response Analysis

- Output response analysis of this adder can be

implemented by a PSA formed by a 16-bit MISR plus

one comparing construct. - The characteristic polynomial of this MISR is

f(x) x16 x5 x3 x2 1, the structure of

which refers to the following figure, where n

16, h5 1, h3 1, h2 1 and all other hi equal 0

for this case. - The MISR takes outputs from the adder and

compacts their responses into one vector called

signature of this input sequence. - The expected signature can be obtained in advance

by software simulation and then put into the

comparing construct, at which it will be compared

with the real output from the MISR when doing the

BIST test

BIST design of the two adders

- The two 16-bit adders in our circuit under test

will be tested in parallel. - Altogether, there is one TPG, two MISRs, one

Comparing Construct and one Test Controller. - When the test starts, under the control of the

Test Controller, firstly the test patterns

generated by the TPG will be sent to the two

adders respectively. Then, the two output

sequences from the two adders will be sent into

two independent MISRs, and the final results from

these two MISRs will be sent into the comparing

construct at the same time and a final test

report will be given after the comparisons.

Test Architecture

Test Process

- There are three input signals for the test

controller the system clock signal, the system

asynchronous reset signal and the synchronous

testmode signal. - The testmode signal is used to select the

working mode for the system, 0 for the normal

working mode and 1 for the test mode. - At the active edge of the system clock, if the

testmode signal equals 1, the system will

enter the self-test mode and the normal work will

be postponed, otherwise the system will enter the

normal working mode. - Two additional output signals are added into the

system for the self-test test_done signal

shows the end of the test when it turns into 1

and test_report signal tells if there is any

fault with these two adders when the test ends. - The whole test period is 326 test clock cycles.

Contents

- 1. Introduction
- 2. BIST Related Technologies
- 3. BIST Design of the Calculation Logic
- 4. Design Implementation Verification
- 5. Conclusion

Design implementation

- EDA tool Active-HDL, ISE of Xilinx
- Language VHDL
- Design level Gate Level
- Synthesis Into a FPGA SPARTAN-IIE of Xilinx

Design verification

- Logic simulation
- EDA tool Active-HDL
- Waveforms
- Fault simulation
- EDA tool Verifault of Cadence
- Verilog files

Logic simulation

- Logic simulation of this design is executed in

Active-HDL by means of waveform. - The design finally passes both the unit test and

the integrated test. - In the following section, we will see some

important simulation results in terms of

waveform.

Simulation of 4-bit External XOR LFSR

- We can see in the waveform that this 4-bit LFSR

can generate all the 15 numbers within the range

of 1 to 15 periodically at each active edge of

the clock when the enable signal is on and that

is exactly what we need.

Simulation of TPG

- In this waveform, the signal counter_2 is used

to count the number of the test patterns

generated and we can see there are 324 test

patterns altogether, which is the same as what we

calculate above.

Simulation of Signature Generator

- Signature Generator is used to generate the

expected signature for the ORA. We can see in the

figure that the expected signature is x5C84

Simulation of the whole system

- After 326 test clock cycles when the self-test

starts, the test_done signal turns to 1,

which shows the end of the test, and the

test_report signal remains 0, which means

there is no fault in the circuit under test. - The signals result1 and result2 represent the

outputs from the two MISRs and we can see in the

waveform they both equal x5C84 at the end of the

test, which are the same as the expected

signature, and that also means there is no fault

in the circuit and that is why we can get the

test_report with 0. - So the whole system is proved to be functionally

correct.

Fault Simulation

- Fault simulation is used to verify if the test

pattern we offer for the BIST can get the

expected fault coverage. - The basic idea of the fault simulation tool is

that the user offers the tool the netlist of the

circuit, which describes the structure of the

circuit, the test patterns used to test the

circuit, and some configuration information, and

then the tool will give the user some reports,

which will tell the user what is the fault

coverage for this circuit with the offered test

patterns for specific fault models. - The fault simulation tool we suppose to use is

Verifault-XL from Cadence. And this tool only

takes the Verilog type of netlist. So in order to

use this tool, we have to write the Verilog-type

netlist for our VHDL codes first with help of

Design Compiler from Synopsys. A Verilog program

is also needed to call the system functions of

Verifault in order to perform the fault

simulation. - Yet we can not do fault simulation this time

because the tool Verifault is not ready. We will

try to do it later when the tool is available.

Contents

- 1. Introduction
- 2. BIST Related Technologies
- 3. BIST Design of the Calculation Logic
- 4. Design Implementation Verification
- 5. Conclusion

Conclusion

- The most important part the BIST design to find

the suitable test patterns for the circuit under

test that can achieve the required the fault

coverage. - There are many implementation methods for the

TPG, among which LFSR is the most widely used one

because it is simple and not easy to add extra

faults to the CUT, which is a big concern for the

BIST design. - The LFSR supposed to be used for the generation

of the test patterns for the 4-bit CLA is

improved from a 9-bit LFSR to a 4-bit LFSR adding

a 5-bit shift register, dramatically shortening

the test period. - The two adders in the CUT are tested in parallel

which shortens the test period. - Finally, our design is implemented in VHDL,

synthesized into an FPGA, and fully verified

through logic simulation in terms of waveforms.

THE END

Thank you.