VHDL to PlaceandRoute Design Flow Tutorial

1
VHDL to Place-and-Route Design Flow Tutorial
Mississippi State University Dallas Semiconductor

• By Wei Lii Tan
• Advisor Dr. Robert Reese
• This revision October 30, 2001

2
Major Changes in This Revision

• Added explanation for Display Options and Find
  forms.
• Added section on checking for shorts between VDD
  and GND in the ICFB section.

3
Introduction

• This tutorial will guide you through the
  synthesis of a fully placed-and-routed design
  from a VHDL entity.
• The tutorial will use the following CAD tools
• - Synopsys Design Compiler
• - Cadence Design Planner
• - Cadence Silicon Ensemble
• - Cadence ICFB
• - Modelsim QHDL

4
Introduction

• The following conventions will be used in this
  tutorial
• - File names will be in italics, e.g.
  /ccs/issl/micro/users/tan/myfile.vhd
• - User input (e.g. what you need to type) will
  be in boldface, e.g. type swsetup cadence-ncsu
• It is highly recommended that you go through the
  no pads tutorial before you start on this one.

5
The Example Design

• The design we will be using as an example for
  this tutorial is a VHDL model of a Dallas
  Semiconductor DS1620k temperature sensing kit.
• The interface reads the temperature from the
  DS1620k, then outputs the data to a seven-segment
  digit display.
• The design also includes some simple gates for
  debugging, such as a NAND gate, NOR gate,
  inverter, and a DFF.
• A simple counter is included in the design too.

6
The Example Design

• The main top-level signals in the design are
• inv_in, inv_out input and output for simple
  inverter
• nand2in_a, nand2in_b, nand2_out inputs and
  output for simple NAND gate.
• nor2in_a, nor2in_b, nor2_out inputs and output
  for simple NOR gate.
• _csb_6_ to _csb_0_ Signals for MSB of the
  seven-segment digit display.
• _lsb_6_ to _lsb_0_ Signals for LSB of the
  seven-segment digit display.

7
Copying Example Files

• Copy the entire directory /ccs/issl/micro/users/ta
  n/tutorials/design_flow into your work directory
• importantAll directories will start with
  your_work_directory/design_flow, unless specified
  otherwise.

8
Design Flow
VHDL Model
VHDL -gt Verilog Conversion
Synopsys Design Compiler
Verilog Model
Verilog Verification
Modelsim
Verilog Model
Standard Cell Placement
Cadence Design Planner
DEF File
Standard Cell Routing
Cadence Silicon Ensemble
DEF File
Export to Other Formats, SPICE Verification
Cadence ICFB
Verilog Model
Verilog Verification
Modelsim
9
Synopsys Design Compiler

• This tool will convert a VHDL model to a Verilog
  model. It requires the use of the following
  user-provided files
• - Library file, in .db format.
• - Script file (file extension .script)
• - The VHDL file to be converted to Verilog.
• At this stage, we will be using Design Compiler
  to generate a Verilog model, without pads, of a
  VHDL file called topchip_gold_pads.

10
Synopsys Design Compiler

• The VHDL file that we will be using is
  topchip_pads.vhd.
• Using a script file with Design Compiler, we will
  convert this VHDL model to verilog.
• The script file is called topchip_pads_int.script,
  and can be found in the synopsys/run_syn
  directory.

11
Why use a script file?

• Using a script file with dc_shell is equivalent
  to typing the exact commands in dc_shell
  interactively.
• A script file automates the process of typing in
  all the commands manually.

12
What is the .db file for?

• The database (.db) file holds information about
  the standard cell library used to implement the
  VHDL design.
• It provides information about the standard cells
  the names of the standard cells, input/output
  ports, as well as timing characteristics and
  functionality.

13
Design Compiler

• Change to the directory synopsys/run_syn
• Type swsetup synopsys
• Type dc_shell f topchip_pads_int.script
• The -f option tells design compiler to use a
  script file, and not run in interactive mode.
• 5. After design compiler finishes (it should take
  about 5 minutes to finish the compilation), a
  verilog netlist file called topchip_pads.v should
  be created in the directory synopsis/gate.

14
Getting Rid of Unwanted Characters

• Cadences family of CAD tools have strict rules
  about naming ports and nets. Therefore, we need
  to get rid of some unwanted symbols in our
  Verilog netlist, so that we wont run into
  problems further down the road, when using the
  Cadence Tools.
• Symbols like front-slashes, back-slashes, and
  other numerical operators are not allowed in net
  names, if you are using Cadence tools.

15
Getting Rid of Unwanted Characters

• Change to the synopsys/gate directory.
• Run the perl script called myfilter.pl on the
  verilog netlist file, by typing
• perl myfilter.pl topchip_pads_int.v
• 8. This will filter out all the unwanted
  characters from the netlist file.

16
Adding I/O Pads (Synopsys Design Compiler)

• Using another script file (topchip_pads.script),
  we will add I/O Pads to the verilog netlist
  topchip_pads_int.v.
• 10. Type dc_shell f topchip_pads.script
• 11. This will generate another verilog netlist
  file, topchip_pads.v, in the directory
  synopsys/gate.

17
Making Other Changes

• Design Compiler will add input and output pads
  automatically, but we still need to add the VDD,
  GND and bi-directional and no-connection Pads
  manually.
• Go to the /synopsys/gate directory.
• Using any text editor, open up the file
  topchip_pads.v for editing.

18
Adding Other Pads

• Add in these pad declaration lines (somewhere
  before the endmodule line).
• PAD_BIDIRHE MY01 ( .DO(ds_dqout), .DI(ds_dqin),
  .OEN(tri_direction),
• .YPAD(ds_dq))
• PADVDD MY02 ( .vdd(vdd), .YPAD(vdd_pad))
• PADNC MY03 ()
• PADGND MY04 ( .gnd(gnd), .YPAD(gnd_pad))
• PADNC MY05 ()

19
Adding Other Pads

• The Cadence PR tools will not auto-route the vdd
  and gnd I/O pins to the supply rings, no matter
  what name you give their ports in the verilog
  netlist. We will have to do this by hand later on
  in ICFB.
• The two PADNC pads are there just to fill in
  extra space (we are using a 40-pad square
  padframe, therefore we need 10 pads on each side).

20
Changes to Module Ports

• We now need to modify the module ports in the
  verilog netlist.
• Delete the nets ds_dqin, ds_dqout, and
  tri_direction from the module port declaration.
• Add the net ds_dq to the module port declaration.
• Delete the net ds_dqin from the input
  declaration.
• Delete the nets ds_dqout and tri_direction from
  the output declaration.
• Add an inout declaration with the net ds_dq.
• Refer to the next slide for details

21
Changes to Module Ports

• module topchip_pads ( inv_in, inv_out, nor2in_a,
  nor2in_b, nor2_out, nand2in_a, nand2in_b,
  nand2_out, dff_out, dff_in, ds_dqout, ds_dqin,
  tri_direction, led_a, led_b, switch_control,
  count_enable_not, clk, msb_dp, lsb_dp, _csb_6_,
  _csb_5_, _csb_4_, _csb_3_, _csb_2_, _csb_1_,
  _csb_0_, _lsb_6_, _lsb_5_, _lsb_4_, _lsb_3_,
  _lsb_2_, _lsb_1_, _lsb_0_, resetn, ds_rn,
  output_rdy, clk_out, ds_dq )
• input inv_in, nor2in_a, nor2in_b, nand2in_a,
  nand2in_b, dff_in, ds_dqin, switch_control,
  count_enable_not, clk, resetn
• output inv_out, nor2_out, nand2_out, dff_out,
  ds_dqout, tri_direction, led_a, led_b, msb_dp,
  lsb_dp, _csb_6_, _csb_5_, _csb_4_, _csb_3_,
  _csb_2_, _csb_1_, _csb_0_, _lsb_6_, _lsb_5_,
  _lsb_4_, _lsb_3_, _lsb_2_, _lsb_1_, _lsb_0_,
  ds_rn, output_rdy, clk_out
• inout ds_dq

Add
22
Sample File with Changes Implemented

• The file synopsys/gate/topchip_pads_sample.v
  contains all the changes that we talked about in
  the previous slides.
• You can use that file as a reference on what to
  change in the verilog netlist, or simply copy it
  over your topchip_pads.v file if you dont feel
  like making the changes yourself.

23
Modelsim

• The next step in the design flow is simulating
  the verilog netlist that we generated.
• Change to the qhsim directory, and type swsetup
  modelsim.
• If the qhsim/work directory does not exist,
  create one by typing qhlib work.
• - The qhlib work command creates a directory
  called work, and also stores Modelsim
  information in the work directory. This
  directory will be the object directory for
  standard cells and top-level designs that are
  compiled using Modelsim.

24
Modelsim

• Before we compile our top-level design
  (topchip_pads.v), we need to compile the standard
  cells that make up topchip_pads.v. In the qhsim
  directory, type
• qvlcom ../synopsys/gate/libcells.v.
• 4. Type
• qvlcom ../synopsys/gate/topchip_pads.v. This
  will compile our top-level design file.
• 5. Now, type
• qvlcom ../synopsys/gate/tb_topchip_pads.v. This
  will compile the testbench for our design. The
  testbench supplies input vectors needed to test
  the functionality of our design.

25
Modelsim

• To enter Qhsim and simulate our design, type
  qhsim tb_topchip_pads. Note that the argument
  after the qhsim command refers to the Verilog
  module name of our design, not the file name.
• After you do step 6, you should see a screen that
  looks like Figure 1. In the command window, type
  view signals ltentergt and view wave ltentergt. These
  commands bring up the signals and waves windows
  respectively.

26
Figure 1 Modelsim Command Window
27
Modelsim

• 8. Go to the signals window, click on view -gt
  wave -gt signals in region. This will add all the
  top-level signals to the wave window.
• 9. Type run 150 us in the command window. This
  will run the testbench for 150 microseconds.
• 10. Note that all the commands that you entered
  in the command window can be entered into a text
  file, then recalled by typing do filename in the
  command window.

28
Figure 2 Simulation Results Waveform
29
Getting Ready to Import into Design Planner

• Now that we have verified that the Verilog
  netlist works properly, lets import the Verilog
  netlist into Cadence Design Planner.
• Copy the file topchip_pads.v from the directory
  synopsys/gate to the directory cadence/dp_se/netli
  st.

30
Starting Design Planner

• Change to the directory cadence/dp_se.
• From this directory, the main subdirectories are
  
• run This will be the directory to invoke all of
  the Design Planner tools.
• tech Contains the tech.dpux file.
• netlist contains the gate level verilog netlist

31
Starting Design Planner

• (continued from previous page)
• design_db_ami06 Contains the pillar database
  of the design
• jennings_ami06_pads_noqn Contains the pillar
  database of the standard cells.

32
Starting Design Planner

• 3. Change to the run directory.
• 4. Type swsetup cadence-dp
• 5. Type areaPdp tech ../tech . This will
  invoke the Design Planner. You should see two
  windows the Pillar window, and the AreaPdp PCW
  log window.

33
Importing the Netlist

• 1. In the Pillar window, click on
• File -gt Import -gt Verilog
• 2. Wait for the ver2hld form to show up - it may
  take a couple of minutes to show up, and clicking
  on other menu items at this time may cause the
  program to crash.

34
Importing the Netlist

• 3. In the ver2hld form, type in
  ../netlist/topchip_pads.v for input verilog
  filename.
• 4. Check the run translation box, and type
  topchip_pads for name of top cell.
• 5. Check the name of global nets box, and type
  vdd for power, gnd for ground.

35
Importing the Verilog Netlist into Design Planner

• 6. In the ver2hld form, check the tie nets (up
  down) box, and enter vdd gnd for that field.
• 7. Type in design_db_ami06 for the output
  library name.
• Make sure the Create Pins for Top Layer of Cell
  box is NOT checked.
• Click on OK. This will generate an AutoLayout
  view for topchip_pads.v.

36
Figure 3 Ver2hld form
37
Floorplanning (Design Planner)

• 1. In the Pillar window, click on
• File -gt Explore Libraries
• 2. In the browse libraries form, double click on
  design_db, topchip_pads, then autoLayout.
• 3. The areaPdp main edit window will show up.
  Notice that all blocks and cells are placed at
  the origin (0,0).

38
Figure 4 topchip_pads autoLayout, before
Floorplan Initialization
39
Initializing the Floorplan (Design Planner)

• 1. In the areaPdp edit window, click on Floorplan
  -gt Initialize
• 2. The Initialize Floorplan form will appear.
  Estimate aspect ratio will determine the aspect
  ratio of the design any value other than 1.0
  will generate a rectangular design, while 1.0
  will generate a square design.

40
Initializing the Floorplan (Design Planner)

• 3. Enter 110 for I/O Circuit to Core Dist
• 4. Make sure that the Move-Fixed box is checked,
  and the None box is not checked.
• 5. Click the Apply Close button.

41
Figure 5 After Floorplan Initialization
42
Placing Pads (Design Planner)

• 1. In the areaPdp window, click on
• Place -gt I/O -gt Pads/Pins
• 2. A form will appear. Select the following
  selections for the form fields
• I/O Init Module Print Random Io File
• I/O Init Filename ioPlace
• I/O Init File Format normal

43
Placing Pads (Design Planner)

• I/O Init I/O Boundary Mode
• Generate new
• I/O Init I/O Side Ordering
• BL-gtR RB-gtT TR-gtL LT-gtB
• 3. Click on the Apply button. This will generate
  a file called ioPlace that contains I/O cell
  placement information.

44
Placing Pads (Design Planner)

• 4. Now that the ioPlace file has been generated,
  we will proceed to actually place the I/O pads
  with the information contained in the ioPlace
  file.
• 5. Change I/O Init Module to Load File Auto
  Place
• 6. Change I/O Init I/O Boundary Mode to Maintain
  Existing

45
Placing Pads (Design Planner)

• 7. Click on the Apply Close button.
• 8. In the areaPdp edit window, you should see the
  top layer pins placed evenly on all four sides of
  the boundary.

46
Figure 6 Place I/O Form
47
Figure 7 After Pads Placement
48
Getting The Correct Pad Orientations

• When the pads are placed, their orientation will
  be incorrect.
• For each pad, highlight the pad and press shift-r
  twice. This will orientate the pads correctly
• A small triangle marks the top-right corner of
  the pad (this is true for all other cells too).
  Use this triangle to help determine if the pads
  are in correct orientation.

49
Figure 8 Incorrect vs. Correct Pad Orientation
Incorrect Orientation
Correct Orientation
50
Placing Corner Pads

• 1. In the areaPdp edit window, click on
• Place -gt I/O -gt Corner Cells -gt Add
• 2. Once the add corner cells form shows up, click
  on all 4 of the I/O Corner BL, I/O Corner BR,
  I/O Corner TL and I/O Corner TR boxes.

51
Placing Corner Pads

• You can use the Browse button to select the
  correct corner pad, or you can simply type in
  your selection in the boxes.
• Type in the following for all four corner pads
• Library Name Jennings_ami06_pads_noqn
• Cell Name padfc
• View Name abstract

52
Placing Corner Pads

• Select R0, R90, R180 and R270 for BL, BR, TR and
  TL orientation respectively.
• Click on the Apply Close button.

53
Figure 9 After Corner Pad Placement
54
Placing Corner Pads

• You may notice that Figure 9 show more layers
  than just the cell boundary. To show more layers,
  go to the View -gt Preferences menu
• Next, drag the levels bar all the way to the
  right.

55
Getting the Correct Corner Pad Orientation

• As shown in Figure 9, the orientation for the
  four corner pads are wrong.
• To fix this, click on a corner pad, then press
  shift-r once. This should set the pad in correct
  orientation.
• Do the same for all corner pads.
• Save your design as pads by clicking on File -gt
  Save as , then typing pads for the save
  filename.

56
Figure 10 Correct Corner Pad Orientation
57
File-Save Woes

• Note If you are using an xterm connection to run
  Design Planner (i.e. you are not using a UNIX
  machine), Design Planner will have a tendency to
  freeze when saving files. Unfortunately you
  cannot do anything about this, except to save
  often, so that if Design Planner happens to
  freeze while you are saving a file, you can
  always go back to your last saved version.
• You can also try using save instead of save
  as. The save command usually will not cause
  the program to crash. This will overwrite the
  previous file, though.

58
Creating Supply Rings (Design Planner)

• 1. In the areaPdp window, click on
• Floorplan -gt Preroutes -gt Supply Rings
• 2. The create supply rings form will appear.
• 3. Click on Nets Named. Type vdd gnd for the
  names.
• 4. Select Area for ring mode. Check Snap to grid.

59
Creating Supply Rings (Design Planner)

• 5. Now we will enter the characteristics for the
  horizontal and vertical ring layers. For LayerH,
  select met1, type in 4.5 4.5 for width(s) and
  3 3 for spacing(s).
• 6. For LayerV, select met2, type in 4.5 4.5 for
  width(s) and 3 3 for spacing(s).
• 7. This will create supply rings for vdd and gnd
  4.5 units wide, with 3 units spacing in between,
  using metal 1 for the horizontal ring portions
  and metal 2 for the vertical ring portions.

60
Figure 11 Route Rings Form
61
Creating Supply Rings (Design Planner)

• 8. Click on the Apply Close button.
• 9. The mouse cursor will change into a crosshair.
  Click on the top left corner of the ring, then
  the bottom right corner. The positions you click
  will be used as the inner positions of the supply
  ring, so be sure to leave some space outwards of
  the positions you click on.
• You should now be able to see the supply rings
  in the areaPdp window.
• Save your file as supply_rings.

62
Figure 12 After Creating Supply Rings
63
Creating Region of Rows (Design Planner)

• In the areaPdp window, click on
• Floorplan -gt Rows -gt Create region of rows
• 2. Set Site Name as core.
• 3. Set Row orientation as Horizontal.
• 4. Uncheck the Number of rows box.
• 5. Check Channel Offset, and set offset to 0.0
• 6. Check Site Orient Pattern and set Orient to
  R0.
• 7. Set Pattern to R0 MX.
• 8. Check the Abutted box.

64
Figure 13 Draw Site Region Form
65
Creating Region of Rows (Design Planner)

• Click the Apply button.
• The mouse cursor should change into a crosshair.
  Click the top left corner of the region to be
  created, then click the bottom right corner. The
  region should be placed somewhere inside the pad
  frame, within the supply rings.
• 11. A region of rows is created this is where
  the single height logic cells will be placed.

66
Creating Region of Rows (Design Planner)

• Now, change Site Name to dbl_core.
• 13. Repeat the process for the dbl_core rows. Try
  to get the dbl_core and core rows to overlap as
  closely as possible design planner will
  automatically snap them into place.
• 14. This will create a region of rows for
  double-height cell placement.
• 15. Save your design as rows.

67
Creating Region of Rows (Design Planner)

• Note about creating rows
• Try to have both the core and dbl_core regions
  overlap each other exactly. If they dont, Design
  Planner might crash when you are placing the
  cells.
• You can zoom into an area (right-click and drag)
  or out of an area (left-click the zoom out button
  on the right of the editing window), even while
  you are placing the rows.
• You can also pan left, right, up or down when
  placing the rows. Click on the arrow buttons to
  the right of the editing window.

68
Creating Region of Rows (Design Planner)

• You should first zoom in to the top-left corner
  of the region of rows when your cursor looks like
  a crosshair.
• Then left click once on the top-left corner of
  the region of rows.
• Zoom out so you can see the entire region, the
  zoom into the bottom right corner.
• Left click again on the bottom right corner of
  the region of rows.
• This should allow you to place overlapping
  regions easily.

69
Figure 14 After Creating Region of Rows
70
Qplace (Design Planner)

• The next step is to use Qplace to automatically
  place standard cells within the pad frame, inside
  the region of rows we created earlier.
• 1. In the areaPdp window, click on
• Place -gt Blocks/Cells (Qplace)
• 2. Leave the settings as the defaults, then click
  on Apply and Close.

71
Figure 15 Qplace Sequencer Form
72
Qplace (Design Planner)

• This process may take a few minutes. After that,
  the standard cell blocks should be placed inside
  the region of rows.
• If the region of rows you created earlier was too
  small for the cells to fit, an error message will
  be generated and Qplace will fail.
• After Qplace succeeds, save your design as
  qplaced.

73
Figure 16 After QPlace
74
Exporting to DEF Format (Design Planner)

• 1. In the areaPdp window, click on
• Interfaces -gt Silicon Ensemble -gt Export -gt DEF
• 2. In the hld2def form, specify an output
  filename for the DEF file. This should go into
  the Output Def File Name slot. Include the
  desired path for the target file too.

75
Exporting to DEF Format (Design Planner)

• 3. Type ../def_files/topchip_pads_qplaced.def
  for the Output Def File Name.
• 4. Set the DEFOUT Library Name to
  design_db_ami06.
• 5. Type in topchip_pads for DEFOUT Cell Name.
• 6. Type in qplaced for the DEFOUT View Name.
  DEFOUT will use this saved file to generate the
  Def file.

76
Exporting to DEF Format (Design Planner)

• 7. Fill in the rest of the options according to
  Figure 17, on next slide.
• 8. Click on OK.
• 9. This will generate the Def file
  cadence/dp_se/def_files/topchip_pads_qplaced.def

77
Figure 17 hld2def form
78
Why export to DEF?

• The DEF format is Cadences method of
  transporting designs from one Cadence CAD tool to
  another.
• DEF stands for Design Exchange Format. You will
  need to export to DEF when transferring a design
  from Design Planner to Silicon Ensemble, or from
  Silicon Ensemble to ICFB.

79
Silicon Ensemble

• We will now move on to using Silicon Ensemble to
  complete the design flow.
• 1. Quit AreaPdp by closing the Pillars window.
• 2. Make sure that you are in the
  cadence/dp_se/run directory.
• 3. In the terminal window, type
• swsetup cadence-se
• sedsm
• This will start Silicon Ensemble.

80
Importing the LEF File (Silicon Ensemble)

• 1. In Silicon Ensemble, click on File -gt Import
  -gt LEF.
• 2. In the Import LEF form, select the file
  ../tech/jennings_ami06_pads_noqn.lef, then click
  on OK.

81
Importing the LEF File (Silicon Ensemble)

• 3. In the Silicon Ensemble window, click on File
  -gt Import -gt DEF.
• 4. In the Import DEF window, Select the file
  ../def_files/topchip_pads_qplaced.def
• 5. Click on OK.
• 6. If the design does not show up, click on Fit
  in the Silicon Ensemble window to view the design.

82
Figure 18 The Imported DEF File
83
Viewing Layers (Silicon Ensemble)

• To view nets, special wires, pins, cell
  boundaries etc. while you are working on your
  design, make sure all the appropriate Vs
  (visible) fields are checked.

84
Adding Filler Cells (Silicon Ensemble)

• 1. Click on Place -gt Filler Cells -gt Add Cells.
• 2. In the SROUTE Add Filler Cells form, type in
  FILL for Model, and fill for prefix.
• 3. Make sure ONLY the North and Flip South boxes
  are checked.
• 4. In the special pins section, add one entry for
  vdd and one entry for gnd (refer to Figure 19 on
  the next slide)

85
Figure 19Add Filler Cells Form
86
Adding Filler Cells (Silicon Ensemble)

• 5. Click on OK.
• 6. This will add filler cells to your design.
  Filler cells provide n-well continuity for your
  standard cells.

87
Figure 20 After Adding Filler Cells
88
Routing Power (Silicon Ensemble)

• 1. Click on Route -gt Route Power -gt Follow Pins.
• 2. In the Layers section of the Sroute Follow
  Pins form, set Width to 1.80.
• 3. Click on OK.

89
Figure 21 Sroute Follow Pins Form
90
Figure 22 After SRoute Follow Pins
91
Wroute (Silicon Ensemble)

• 1. Click on Route -gt Wroute.
• 2. In the Wroute form, click on OK.
• Wroute will run. This will take a few minutes to
  complete.
• After this point, all the interconnect routing of
  the design has been done.

92
Figure 23 After WRoute
93
Viewing Different Layers in Silicon Ensemble

• You wont be able to see the interconnect metal
  layers in Figure 23 unless you enable the layer
  to be viewable.
• Click on View -gt Layers.
• In the Layer Visibility form, click on All
  Objects, then check all the layer check boxes.

94
Display Options

• Silicon Ensemble allows you to customize the view
  window to display/not display certain parts of
  your design.
• In the main window, click on View -gt Display
  Options

95
Display Options

• Notice the top part of the Display Option form
  allows you to select On, Here, Big, Small etc
  for the Level. By choosing a level here and
  clicking on the checkboxes, the selection for
  that particular checkbox will rotate between
  OFF and the level you chose.
• For example, select Small for the level. Now,
  click once on the Cells checkbox in the Objects
  section.
• If the checkbox was originally set to On, it will
  switch to Off after the first time you click it.
  Click on it again to set it to Small.
• Click on Apply.

96
Display Options

• Your cell boundaries will now only be visible
  when you are zooming into a smaller portion of
  the design.
• If you click on the Fit button in the main
  window, you will not see the cell boundaries any
  more.
• Try zooming into a small area of the design. The
  cell boundaries will be visible again.

97
Display Options

• The following explains the different levels
• - On visible at any level.
• - Here visible at level that is currently
  displayed in the main window.
• - Big, medium, small visible at big, medium or
  small levels respectively.
• - Off not visible at any level.

98
Checking Pin Names

• You can easily check to see the names of the
  routed pins in the standard cells using the
  Display Options form.
• In the Names section of the Display Options form,
  set Pins to On, or Small.
• Click on the Apply button. The pin names will now
  be visible.

99
The Find Form

• You can find cells, nets and pins etc. with the
  Find form. Click on Edit -gt Find to access the
  Find form.
• On the Find form, set Type to Net.
• Type n1022 for the Name.
• Set the background dimmer to 70, then click on
  the Hilight button.
• The display will be dimmed, while the msb_dp net
  will be highlighted in the color selected in the
  Find form.

100
(No Transcript)
101
The Find Form

• You can also give partial names, e.g. n10
  instead of n1022. If you click on the Show List
  checkbox, you will see a list of matching names.
• Type n10 for the net name, click on Show Lists,
  then click on Find. You should see a list of net
  names starting with n10.

102
The Find Form

• You can now click on each individual entry in the
  list, and highlight the particular net, or select
  it.
• The Find form, together with the Display Options
  form, provide a convenient way of debugging your
  overall routed design.

103
Checking for Violations

• Violations will appear as X marks on your
  design. Be sure that there are no violations
  created during the routing.
• Silicon Ensemble will tell you the number of
  violations created during Wroute (Refer to Figure
  24, on the next slide). If there are any
  violations, be sure to fix them before moving on.
  You should not get any violations for this
  exercise.

104
Figure 24 Total Number of Violations Reported by
Silicon Ensemble
105
Export to DEF Format (Silicon Ensemble)

• 1. Click on File -gt Export -gt DEF.
• 2. Type ../def_files/topchip_pads_wrouted.def
  for the DEF file name.
• 3. Make sure the All checkbox is checked.
• 4. Click on OK.
• This will create the DEF file cadence/dp_se/def_fi
  les/topchip_pads_wrouted.def.

106
Running SEDSM in Script Mode

• When using SEDSM in interactive mode (like we
  just did), SEDSM will echo back your commands in
  the command-line window.
• If you enter these commands into a text file, you
  can run SEDSM in script mode. To run SEDSM in
  script mode, type the following in the
  cadence/dp_se/run directory
• sedsm b gdansi EXECUTE script.mac
• where script.mac is the name of your script file.

107
Running SEDSM in Script Mode

• The cadence/dp_se/run directory has a script file
  called topchip_pads.mac which will essentially
  perform all the procedures we did in interactive
  mode, from importing the LEF file to exporting
  the topchip_pads_wrouted.def file.
• To execute the script file, go the the
  cadence/dp_se/run directory, and type
• sedsm b gdansi EXECUTE topchip_pads.mac

108
Re-running SEDSM after a Crash

• If Silicon Ensemble crashes while you are running
  it, you need to delete all the .dtp files in the
  cadence/dp_se/run directory before you run it
  again. The .dtp files are the lock files for
  Silicon Ensemble

109
Adding Pin Placement via Perl Script

• Before importing the DEF file into ICFB, we need
  to add top-layer pin placement to the file
  topchip_pads_wrouted.def.
• Go to the cadence/dp_se/def_files directory.
• Type perl insert_pads.pl topchip_pads_wroute
  d.def
• This perl script, written by Dr. Robert Reese,
  will automatically place top-layer pins in the
  correct positions (on top of their respective
  YPAD ports) by modifying the PINS section of the
  DEF file.

110
Cadence ICFB

• Cadence ICFB is the last CAD tool in this design
  flow. In ICFB, our design can be exported into a
  HSpice netlist, a Verilog netlist, or GDSII / CIF
  formats, among others.
• Cadence ICFB is potentially the most powerful CAD
  tool among the tools in this design flow, but it
  is also the most complex.

111
Starting ICFB

• If youve previously used Design Planner or
  Silicon Ensemble in your current xterm window,
  launch a new xterm window.
• Change to the cadence/dfII directory.
• Type swsetup cadence-ncsu.
• Type icfb to launch ICFB.
• You should see three windows pop up the ICFB
  Command Interpreter Window (CIW), the Library
  Manager window, and another windows telling you
  about the changes for the latest version of ICFB.
  Close the third window.

112
Importing DEF into ICFB

• In the CIW, click on File -gt Import -gt DEF.
• Enter tutorial for Library Name, topchip_pads
  for Cell Name, and autoRouted for View Name.
• Enter ../dp_se/def_files/topchip_pads_wrouted.def
  for DEF File Name.
• Make sure Silicon Ensemble is checked.
• Refer to Figure 25 (next slide) for all other
  options in the form.

113
Figure 25 Import DEF Form
114
Figure 26 topchip_pads autoRouted view
115
Importing DEF into ICFB

• Open the autoRouted view of topchip_pads.
• In the autoRouted view, before you do anything,
  click on Design -gt Save. This ensures that if
  anything goes wrong, you can always come back to
  the autoRouted view.
• Click on Tools -gt Layout. This changes the tool
  from abstract-editing mode to layout-editing mode.

116
Importing DEF into ICFB

• Click on Edit -gt Search
• In the Search form, search for inst in current
  cellview, with view name abstract. Replace with
  view name -gt layout. (Refer to Figure 27, next
  slide).
• Click on Apply, then Replace All.
• Close the search form, then click on Design -gt
  Save as
• Save the design in the same library and cell, but
  change the view to layout.
• When you close the editing window, you will be
  asked if you want to save changes for the
  autoRouted view. Do not save any changes here or
  the autoRouted view will be over-written.

117
Figure 27 Search Form
118
Viewing Layers in ICFB

• Whenever in ICFBs layout editor, you can press
  shift-f to increase the number of layers viewed,
  or ctrl-f to decrease the number of layers
  viewed.
• For example, if you press shift-f while viewing
  the topchip_pads layout, you will be able to see
  the metal, poly, active etc. layers of the
  individual standard cells. If you press ctrl-f,
  you will only be able to see the boundaries of
  the individual standard cells.

119
Figure 28 topchip_pads layout view
120
Before You Start

• This section attempts to briefly teach you a few
  basics of ICFB layout editing, namely selecting
  layers, drawing rectangles and copying objects.
• These methods will be employed later in the
  Extracting a Verilog Netlist section.
• If you are already familiar with the basics of
  ICFB, feel free to skip this section.

121
ICFB Layout Basics

• In the Library Manager window, make sure the
  tutorial library is selected.
• Select File -gt New -gt Cellview from the menu bar.
• Fill in the options as shown in the figure below.

122
ICFB Layout Basics

• A new layout window should pop up.
• To draw a metal1.drawing rectangle, select the
  metal1.dg layer from the LSW window (click on it
  once).
• Then, click once on the layout editor window, and
  press r.
• Click once on one corner of the rectangle to be
  drawn, then click once on the opposite corner.

123
ICFB Layout Basics

• To copy the rectangle you just created, press
  esc to exit rectangle drawing mode, then click
  once on your rectangle to select it.
• Press c, then click once on your rectangle,
  then click once on the location you want it to be
  copied to.
• You can experiment with multiple copies by
  changing the row and column values in the
  copy form.

124
ICFB Layout Basics

• The move function is basically the same as the
  copy function, except you press m to activate
  it, instead of c.

125
Connecting PADVDD and PADGND to the VDD and GND
Rings

• Open the layout view of topchip_pads for editing.
• You should default in the Abstract editor. You
  should also see another window, the OSW window
  pop up.
• Click on the AS button of the OSW window. This
  will enable you to select all parts of the design
  (instances, nets, pins etc).

126
Connecting PADVDD and PADGND to the VDD and GND
Rings

• Click on Tools -gt Layout in the layout editing
  window.
• Press ctrl-f once, so that you only see the
  top-layer of the design.
• Click on the inner supply ring once (you might
  have to zoom in a little to make sure). Then
  press q. This will bring up the properties of
  that piece of metal.

127
Connecting PADVDD and PADGND to the VDD and GND
Rings

• Click on the connectivity button once. Then,
  verify that the net name is vdd.

128
Connecting PADVDD and PADGND to the VDD and GND
Rings

• Now, select metal1 (dg) from the LSW window, and
  place a metal1 rectangle from the VDD port of
  PADVDD, to the inner supply ring. Refer to Figure
  29, next slide.

129
Figure 29 Adding the connection from PADVDD to
the VDD ring.
130
Connecting PADVDD and PADGND to the VDD and GND
Rings

• After that is done, copy and place a few more VIA
  instances along the connection region of the
  supply ring and your metal1 rectangle, to provide
  a better connection. (Figure 30, next slide)

131
Figure 30 Adding Extra Vias
132
Connecting PADVDD and PADGND to the VDD and GND
Rings

• Now, repeat the process to connect the GND port
  of PADGND, to the GND supply ring.
• The GND ring should be the outer ring, but you
  should verify that before you continue (by
  looking at the path properties with the q key)

133
Figure 31 Connections for VDD and GND added
134
Extracting a Verilog Netlist

• We need to extract a Verilog netlist out of our
  placed-and-routed design to verify that the
  place-and-route tools did their jobs without
  errors.
• This Verilog netlist will be simulated using
  Modelsim to verify for correct functionality.

135
Extracting a Verilog Netlist

• Before starting this section, change to the
  directory cadence/dfII.
• Then, type
• rm rf topchip_pads.verilog
• This will clear the Verilog netlister work
  directory.

136
Extracting a Verilog Netlist

• After the copy is done, open the Layout view of
  topchip_pads.
• In the layout window, select Tools -gt Layout.
• Now, go to the CIW window (the window labeled as
  ICFB). In the CIW window, type
• load skill_code/cover_pins.il

137
Extracting a Verilog Netlist

• Now, type
• cpins
• in the CIW window.
• 5. This will load the SKILL procedure cpins
  into memory, and run the procedure. This
  procedure adds top-layer metals to pins of the
  I/O pads (this will be discussed further in the
  next few slides). Without this step, macro-cell
  extraction of the design will fail.

138
Figure 32
YPAD port The CPINS procedure will automatically
cover this with an identically shaped metal1
rectangle.
Input/Output port will be covered with an
identically-shaped Metal2 (drawing) rectangle.
139
Figure 33
VDD/GND port. The cpins procedure will cover this
with an identically-shaped Metal1 (drawing)
rectangle.
140
Extracting a Verilog Netlist

• 6. Press ctrl-f to view only top-level objects.
  After running the cpins procedure, the layout
  should look like the Figure 34 (next slide).

141
Figure 34
142
Why do we have to cover all the YPAD and I/O
ports of the pads?

• The macro-cell extractor (which we shall use in a
  minute) expects all ports of all cells to be
  completely covered with a top-level layer. If
  this is not done, the extractor will fail.
• In our originally imported design, the
  input/output ports of the pads were only
  partially covered by the routing metal. The YPAD
  portion of the pads were not covered by any
  top-layer metal routing at all.

143
Extracting a Verilog Netlist

• Now, we need to create an extracted view of our
  design. Open the layout view of topchip_pads.
• Change the editing tool to layout editing by
  clicking on Tools -gt Layout.
• Click on Verify -gt Extract
• Make sure the macro cell box is checked. (Refer
  Figure 35, next slide)
• Click on OK.
• The extraction process will take a few minutes to
  complete.

144
Figure 35 The Extractor Form
145
Extracting a Verilog Netlist

• Click on Tools -gt Verilog-XL. You should see a
  new form called Setup Environment pop up on your
  screen.
• 14. Enter topchip_pads.verilog for the
  simulation run directory.
• 15. Simulate the design in
• Library tutorial
• Cell topchip_pads
• View extracted
• 16. Click on OK. (sample form is on next slide)

146
Figure 36 Setup Environment Form
147
Extracting a Verilog Netlist

• 17. You will see a warning message as shown
  below. Ignore this warning message, since we are
  not going to simulate our design using Cadence.
  We are only going to use ICFB to extract a
  Verilog netlist.

148
Extracting a Verilog Netlist

• The Verilog-XL Integration window will now pop
  up. Click on Setup -gt Netlist
• The Verilog Netlisting Options form will pop up.
  Click on the More gtgt button. This will enable you
  to see all the options for this form.
• For the Netlist These Views field, enter
  behavioral functional symbol verilog.
• For the Stop Netlisting at Views field, enter
  behavioral functional symbol.
• Enter vdd and gnd for Global Power Nets and
  Global Ground Nets, respectively.
• Make sure the netlist explicitly box is checked.
  Then, Click on OK.

149
Figure 37 Verilog Netlisting Options Form
150
Extracting a Verilog Netlist

• Back in the Verilog-XL Integration window, click
  on Simulation -gt Start Interactive.
• The first time you run the verilog netlist
  extraction, you will get two errors regarding
  inherited nets for every instance you have in
  your design (on the order of a few thousand
  errors for our design). Ignore these errors -
  they are internal errors and should be fixed in
  the latest version of ICFB. Click on Simulation
  -gt Start Interactive again you will not get
  these errors the second time.

151
Extracting a Verilog Netlist

• Ignore the warning shown below (click on OK). We
  can ignore this warning because we are not going
  to run Verilog simulation in ICFB.

152
Extracting a Verilog Netlist

• A text file called verilog.inpfiles, located in
  the netlister work directory (cadence/icfb/topchip
  _pads.verilog) is created. This file tells of the
  location of the Verilog netlists generated.
• Using a text editor (pico, VI etc.), view the
  file verilog.inpfiles.
• The text file will tell the location of the
  top-level Verilog netlist it is going to be in
  ihnl/cds?/netlist, where ? will be a number (it
  is probably going to be the number zero).

153
Extracting a Verilog Netlist

• Open the file ihnl/cds?/netlist with any text
  editor.
• 30. Make sure the top-level module name is named
  as topchip_pads (change it to topchip_pads if it
  is not already named so). The testbench that we
  are going to use to simulate the design expects
  that as the module name.

// Library - tutorial, Cell - topchip_pads, View
- extracted // LAST TIME SAVED Jul 30 142700
2001 // NETLIST TIME Jul 30 142839
2001 timescale 1ns / 1ns module topchip_pads (
_csb_0_, _csb_1_, _csb_2_, _csb_3_, _csb_4_,
_csb_5_, _csb_6_, _lsb_0_, _lsb_1_, _lsb_2_,
_lsb_3_, _lsb_4_, _lsb_5_, _lsb_6_, clk_out,
dff_out, ds_rn, inv_out, led_a, led_b,
154
Extracting a Verilog Netlist

• Copy the netlist file from cadence/dfII/topchip_pa
  ds.verilog/ihnl/cds?, to cadence/dfII/gate.
• In the directory /cadence/dfII/gate, rename the
  netlist file to topchip_pads_icfb.v.
• The next section of this tutorial will
  demonstrate how to simulate this Verilog netlist
  using Modelsim. However, before we go into that,
  lets discuss some other issues regarding ICFB.

155
Extracting a Hspice Netlist

• The procedure for extracting a Hspice netlist is
  similar to that of extracting a Verilog netlist,
  up to the Extractor form. There is only one
  difference for the Extractor form
• In the Extractor form, select Flat for Extract
  Method instead of Macro Cell.

156
Extracting a Hspice Netlist

• After running the Extractor form, follow the
  instructions below to generate a HSPICE netlist
• Click on Tools -gt Simulation -gt Other. You should
  see a new menu item - Simulation appear on your
  menu bar.
• 2. Click on Simulation -gt Initialize.
• 3. Enter topchip_pads.hspice for the simulation
  run directory.
• 4. Click on OK.
• 5. Another Initialize Environment form should
  pop-up. This one has the full set of options to
  choose from.

157
Extracting a Hspice Netlist

• In the Initialize Environment form, choose hspice
  for the simulator name.
• Enter Tutorial for Library Name, topchip_pads
  for Cell Name, and extracted for View Name.

158
Figure 38 Initialize Environment Form
159
Extracting a Hspice Netlist

• Go back to the Layout editing window, and click
  on Simulation -gt Options
• Make sure the Use Hierarchical Netlister and
  Re-netlist Entire Design boxes are checked, and
  the others are left unchecked.

160
Extracting a Hspice Netlist

• Go back to the Layout editing window, and click
  on Simulation -gt Netlist/Simulate
• Make sure that the netlist box is checked, and
  the simulate box is not. Also, check the Run in
  background box.
• The remaining information should be already
  filled in correctly for you. Make sure they match
  up to that shown in Figure 39. (next slide)

161
Figure 39 Netlist and Simulate Form
162
Extracting a Hspice Netlist

• Click on OK. Wait for a minute or so as ICFB
  works in the background to generate the Verilog
  netlist.
• A message telling you that the netlister has
  succeeded should pop up after a minute or so.
• The HSPICE netlist will be located in the
  directory that you specified as the run directory
  (for our case, cadence/dfII/topchip_pads.hspice),
  with the filename netlist.

163
Verilog or Hspice?

• For our case, Verilog is a more practical choice.
  
• Verilog is a switch-level language, which means
  it does not model any parasitics of the design.
  This makes simulation much faster than Hspice,
  which models the parasitics of the system.
• Since we started out with a VHDL file, we can
  assume that most of our designs will be
  relatively complex (e.g. having more than a few
  thousand transistors). Hspice simulation for
  designs of this scale is too time consuming.

164
Verilog or Hspice?

• For example, if we were to simulate our
  topchip_pads design using Hspice for 150 us, it
  would take more than 24 hours to simulate.
  Verilog simulation using Modelsim takes less than
  1 second.
• Conclusion Hspice is great for detailed
  simulations (especially for analog systems), but
  for complex, purely digital systems, Verilog
  simulation is much more practical.
• Other simulators such as IRSim fall somewhere in
  between Verilog and Hspice simulators.

165
DRC Verification (ICFB)

• DRC (Design Rule Check) verification checks for
  design rule violations. The NCSU Cadence Design
  Kit comes with a decent (but by no means perfect)
  DRC checker.
• The NCSU kit DRC checker will flag certain metal
  constructs that should not be flagged as errors.
  Refer to the next slide for a more detailed
  explanation.

166
DRC Verification (ICFB)
Metal1 shapes

• The NCSU kit DRC checker will flag these as
  errors if the spacing is less than the minimum
  spacing for that metal layer, even though it
  should not matter because they all belong to the
  same net.

167
DRC Verification (ICFB)

• Open the topchip_pads layout using the layout
  editor.
• Click on Verify -gt DRC
• Check Flat for checking method, and Full for
  checking limit.
• Click OK.
• DRC will run (this will take a few minutes). You
  will get a few thousand of DRC errors, some
  stemming from the false metal error detection
  discussed in previous slides. The other errors
  should be located in the pads (I/O pads seldom
  pass DRC)

168
Figure 40 DRC Form
169
Checking for Short Circuits between VDD and GND

• The easiest way to make your layout fail, is to
  have accidental shorts between VDD and GND.
• Shorts between VDD and GND can easily occur
  during manual layout procedures (e.g. when
  connecting the VDD and GND pads to the supply
  rings).
• Verilog extraction will not detect shorts between
  VDD and GND, because our Verilog simulating
  method ignores the VDD and GND nets.
• Therefore, it is essential to perform a quick
  check to make sure VDD and GND are not shorted.

170
Checking for Short Circuits between VDD and GND

• A simple way to perform this check is to open the
  extracted view of the layout. In the Library
  Manager window, open with extracted view of
  topchip_nopads.
• Now, click on the VDD (or GND) ring. If you
  clicked on the VDD ring, you should see the VDD
  ring, and the VDD rails highlighted. The same
  goes for the GND ring.
• If you see both rings highlighted when you click
  on either ring, then a there is a short from VDD
  to GND in your layout that must be fixed.

171
Exporting to CIF

• Most industrial foundries use a standard design
  transfer file format to send or receive design
  files. CIF is one such format.
• To export to CIF, click on File -gt Export -gt
  CIF
• Enter . for the run directory, tutorial for
  the library name, topchip_pads for the cell
  name, and layout for the view name.

172
Exporting to CIF

• Enter cif_files/topchip_pads.cif for the output
  file.
• Check the CIF DB box.
• Click on OK. This will generate a CIF file called
  topchip_pads.cif in the cadence/dfII/cif_files
  directory.
• You will get some warnings (view the PIPO.LOG
  file) because not all layers in ICFB are
  translated into the CIF file. This is OK.

173
Figure 41 CIF Out Form
174
Modelsim

• The final step in our design flow is to simulate
  our ICFB-generated Verilog netlist using
  Modelsim.
• If the place-and-route procedures were
  successful, we should get the same results for
  this simulation as the simulation we ran with our
  Synopsys-generated Verilog netlist.

175
Modelsim

• There should be the following Verilog files in
  the cadence/dfII/gate directory
• topchip_pads_icfb.v, which we just created,
• tb_topchip_pads_icfb.v, the testbench file for
  the file above.

176
Modelsim

• Change to the qhsim directory.
• Type swsetup modelsim.
• 3. Type qvlcom ../cadence/dfII/gate/libcells_icfb.
  v
• 4. Type qvlcom ../cadence/dfII/gate/topchip_pads_i
  cfb.v
• 5. Type qvlcom ../cadence/dfII/gate/tb_topchip_pad
  s_icfb.v

177
Modelsim

• 5. Type qhsim tb_topchip_pads . This will invoke
  Qhsim to simulate the testbench.
• There is a .do file in the qhsim directory that
  displays the signals and wave windows, adds all
  the top level signals into the wave window, and
  runs the simulation for 150 us. Activate the
  script by typing do tb_topchip_pads.do in the
  command window. If you open up that .do file you
  will find that it contains the same commands that
  you would type in the command window to achieve
  the same results.

178
Modelsim

• 7. Verify that the results for this simulation
  match that of the first Verilog simulation in
  this tutorial, by looking at the wave window.

179
Figure 42 Simulation Results Waveform