Overview

1
Overview

• 5.1 Synchronous Systems with crash failures
• 5.2 Synchronous Systems with byzantine failures
• 5.3 Impossibility in asynchronous Systems

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The 3 cases

• Shared Memory Wait Free Case
• Shared Memory General Case
• Message Passing

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S.M. - Wait free case

• Situation of n gt 1 processors
• All but one processors might fail
• In a finite execution it is impossible to
  determine if a processor is faulty / nonfaulty
• If the last processor does not find a decicion in
  finite time, a configuration C cannot be found,
  because every configuration is bivalent.

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Lemma

• Lemma 5.15
• C1 and C1 are two univalent configurations. If
  C1 C2 for a processor pi, then C1 is v-valent
  only if C2 is v-valent too.

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Proof

• Proof
• C1 is v-valent, and all processors but pi failed.
  
• Consider an infinite execution from C1
• pi needs to decide.
• Because C1 is v-valent pi must eventually decide
  v.
• We know that C1 C2 -gt C2 is also v-valent!

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Lemma

• Lemma 5.17
• If C is a bivalent configuration, then at least
  one processor is not critical in C.
• Proof (Case 1)
• C is bivalent. Two processors Pi and Pj decide
  for i(C) (0-valent) and j(C) (1-valent). If Pi
  and Pj read from different or the same registers,
  i(j(C)) is the same as j(i(C)) gt i(C) and j(C)
  have the same valences.

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Proof

• Proof (Case 2)
• One Processor writes to shared register, and the
  other reads from it.
• i(C) is when Pi takes a step
• j(i(C)) is when Pi writes to R and then Pj
  reads from it,
• i(j(C)) is 1-valent and i(C) is 0-valent!
• But i(j(C)) i(C) which contradicts Lemma 5.15

8
S.M. The General Case

• Show, that there is no consensus algorithm even
  if only one processor might fail.
• Proof by reduction to the impossibility result of
  the wait-free case

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Impossibility

• To prove impossibility
• assume an algorithm A for n processors and 1
  failure
• Use A as a subroutine to design an algorithm A'
  for 2 processors and 1 failure
• Before we showed A cannot exist ? so A cannot
  exist

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Algorithm A

• By contradiction, assume an algorithm A
• exists, which solves consensus for
• processors q0, q1, , qn-1 with 1 failure.
• each qj has a single shared register Rj which it
  writes and others read initially empty
• code of each qj alternates reads and writes,
  beginning with a read
• each write step of qj writes qj 's entire current
  local state into Rj

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Simulation

• Construct an algorithm for two processors p0 and
  p1 to solve consensus with 1 failure
• Now every pi goes through all qj trying to
  simulate their steps
• At the beginning pi uses its own input as input
  for qj
• Whenever pi simulates a decision step it decides
  on the same value

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Simulation

• How can p0 and p1 stay consistent?
• One step is grouped into a pair, which includes a
  read and the following write operation
• After every step, p0 and p1 need to agree on the
  value of qi

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Agreement

• p0 and p1 have a Flag shared variable and a
  Suggest shared variable of every computation qj
  's k-th pair
• The (k-1)-th pair has been computed
• Pi µ_at_

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Agreement

• p0 and p1 have a Flag shared variable and a
  Suggest shared variable of every computation qj
  's k-th pair
• The (k-1)-th pair has been computed
• Pi calculates the next step and checks if the
  other processor has already made a suggestion for
  the state qi
• If not, pi sets its Flag to 1, else to 0

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Interpret the Flag variable

• If pi s Flag is 1, then pi is the winner
• If both Flags are 0 we consider p0 as the winner
• If one is 0 and one is not yet set, then no
  winner is determined
• If none of the Flags are set, no winner is
  determined
• Not possible that both Flags are 1
• Only in the first two points the k-th pair is
• computed!

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