Instruction Set Architecture (ISA) MIPS review (Ch: 2.1- 2.7, 2.10 4th ed)

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Instruction Set Architecture (ISA)MIPS
review(Ch 2.1- 2.7, 2.10 4th ed)

• Instructions Language of the Computer
• Dr. Khaled El-Ayat

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RISC vs CISC review

• RISC -- Reduced Instruction Set Computer ?
  performance
• fixed instruction length
• load/store architecture
• all operands of ALU instructions must be in
  registers
• limited addressing modes operations ? fewer
  instructions
• Implies
• larger register file
• longer program
• good for pipelining
• simpler control
• CISC Complex Instruction Set Computer ?variable
  instructions

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CISC Ex 80x86 Registers
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CISC Ex x86 Instructions have Variable lengths!
Variability is an issue, but is solved by
MicroArchitecture on all x86 CPUs
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Instruction Set Architecture What Must be
Specified?

• Instruction Format or Encoding
• Location of operands and result
• Data type and Size
• Operations
• Successor instruction
• jumps, conditions, branches

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Typical Operations (rev)
Data Movement
Load (from memory) Store (to memory) memory-to-mem
ory move register-to-register move input (from
I/O device) output (to I/O device) push, pop
(to/from stack)
Arithmetic
integer (binary decimal) or FP Add, Subtract,
Multiply, Divide
Shift
shift left/right, rotate left/right
Logical
not, and, or, set, clear
Control (Jump/Branch)
unconditional, conditional
Subroutine Linkage
call, return
Interrupt
trap, return
Synchronization
test set (atomic r-m-w)
String
search, translate
Graphics (MMX)
parallel subword ops (4 16bit add)
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Basic ISA Classes (rev)

• Accumulator (1 register)
• 1 address add A acc acc memA
• Stack
• 0 address add tos tos next
• General Purpose Register
• 2 address add A B EAA EAA EAB
• 3 address add A B C EAA EAB EAC
• Load/Store
• 3 address add Ra Rb Rc Ra Rb Rc
• load Ra Rb Ra memRb
• store Ra Rb memRb Ra

Registers faster than memory, easier for
compiler, less mem traffic
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MIPS R3000 review Registers

• Registers--32 general purpose registers
• zero (0) 0
• 3 special purpose registers
• PC program counter
• Hi, Lo for multiply and divide
• Word length32 bits
• In memory byte addressable

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MIPS Instruction Formats 3layout of
instruction

• 3 formats R-type (regular)
• I-type (Immediate)
• J-type (Jump)
• R-type 6 fields
• op operation code (6 bits)
• rs 1st register source operand (5)
• rt 2nd register source operand (5)
• rd register destination (5)
• sa shift amount (5)
• function select the variant of operation in op
  field (6)

OP rs rt rd sa funct
OP rs rt immediate
OP Target
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Instruction FormatR-Type

• Example add 8, 17, 18OP00, FUNC40
  
• Other R-type instructionssub 1, 2, 3slt 1,
  2, 3jr ra(31) jump register, for returning
  to the
• calling
  procedure

OP rs rt rd
sa funct
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Instruction Format/I-type

• 4 fields, 32 bits
• Immediate (address ) field 16 bits, holds a
  constant
• Example load word -- lw s1, 50(s2)lw s1,
  48(s2) s1 memory s248
• Other I-type inst.add immediate -- addi 8, 9,
  100branch on equal -- beq 1, 2, 25 goto
  (PC4)100 if 12

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Instruction Format/J-Type

• 2 fields 32 bits
• op 6 bits
• address field 26 bits
• Example j 200 go to location f(4200)
• Other J type inst. jal 200 jump link, goto
  location f(4200) 31(ra) PC 4

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Jump InstructionPsuedo direct addressing

• j label go to label

• Instruction Format (J Format)

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MIPS Addressing Modes fyi

• Register addressing
• operand is in a registere.g. add 8, 19, 18
• Base or displacement addressing
• operand at memory location reg. constant
  (base)e.g. lw 8, 200(19)
• Immediate addressing
• operand constant, in inst.e.g. addi 8, 8, 4
• PC-relative addressing
• address (PC) constant in inst.e.g., bne 8,
  21, Exit
• Pseudodirect addressing jump address PC(31-28)
  (concatenated with) jump constant4

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MIPS Addressing Mode Summary fyi
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MIPS Conditional Branch Instructions

• bne s0, s1, Lbl go to Lbl if s0?s1 beq
  s0, s1, Lbl go to Lbl if s0s1
• Ex if (ij) h i j
• bne s0, s1, Lbl1 add s3, s0,
  s1Lbl1 ...

• Instruction Format (I format)

• Target Address PC 4 (offset 4)

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More Branch Instructions

• Can use slt, beq, bne, and the value 0 in
  register zero to create other conditions
• less than blt s1, s2, Label
• less than or equal to ble s1, s2, Label
• greater than bgt s1, s2, Label
• great than or equal to bge s1, s2, Label

slt at, s1, s2 at set to 1 if bne at,
zero, Label s1 lt s2

• Such branches are included in the instruction set
  as pseudo instructions - recognized (and
  expanded) by the assembler

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MIPS Immediate Instructions

• Small constants are used often in typical code

• addi sp, sp, 4 sp sp 4
• slti t0, s2, 15 t0 1 if s2lt15
• Machine format (I format)

• Constant kept inside the instruction
• Immediate format limits values to the range
  2151 to -215

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LUI used for 32-bit Constants

• To load a 32 bit constant into a register, two
  instructions
• "load upper immediate" instruction LUI
• lui t0, 1010101010101010
• Then must get the lower order bits right, use
  
• ori t0, t0, 1010101010101010

16 0 8
1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010 1010101010101010
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How shift instructions are implemented
Two kinds logical-- value shifted in is
always "0" arithmetic-- on right
shifts, sign extend No arithmetic Left Shift
Overflow result
msb
lsb
"0"
"0"
msb
lsb
Note these are single bit shifts. A given
instruction might request 0 to 32 bits to be
shifted!
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Subroutine Calls Stacks
Stacking of Subroutine Calls Returns and
Environments
A
A CALL B CALL C
C RET
RET
B
A
B
A
B
C
A
B
A
Some machines provide a memory stack as part of
the architecture (e.g., VAX) Sometimes stacks
are implemented via software convention (e.g.,
MIPS) Some machines provide stack support in
hardware (Embedded processor)
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MIPS Software conventions for Registers
0 zero constant 0 1 at reserved for
assembler 2 v0 expression evaluation
3 v1 function results 4 a0 arguments 5 a1 6 a2 7
a3 8 t0 temporary caller saves . . . (callee
can clobber) 15 t7
16 s0 callee saves . . . (callee must
save) 23 s7 24 t8 temporary (contd) 25 t9 26 k0
reserved for OS kernel 27 k1 28 gp Pointer to
global area 29 sp Stack pointer 30 fp frame
pointer 31 ra Return Address (HW)
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MIPS ISA So Far
Category Instr Op Code Example Meaning
Arithmetic (R I format) add 0 and 32 add s1, s2, s3 s1 s2 s3
Arithmetic (R I format) subtract 0 and 34 sub s1, s2, s3 s1 s2 - s3
Arithmetic (R I format) add immediate 8 addi s1, s2, 6 s1 s2 6
Arithmetic (R I format) or immediate 13 ori s1, s2, 6 s1 s2 v 6
Data Transfer (I format) load word 35 lw s1, 24(s2) s1 Memory(s224)
Data Transfer (I format) store word 43 sw s1, 24(s2) Memory(s224) s1
Data Transfer (I format) load byte 32 lb s1, 25(s2) s1 Memory(s225)
Data Transfer (I format) store byte 40 sb s1, 25(s2) Memory(s225) s1
Data Transfer (I format) load upper imm 15 lui s1, 6 s1 6 216
Cond. Branch (I R format) br on equal 4 beq s1, s2, L if (s1s2) go to L
Cond. Branch (I R format) br on not equal 5 bne s1, s2, L if (s1 !s2) go to L
Cond. Branch (I R format) set on less than 0 and 42 slt s1, s2, s3 if (s2lts3) s11 else s10
Cond. Branch (I R format) set on less than immediate 10 slti s1, s2, 6 if (s2lt6) s11 else s10
Uncond. Jump (J R format) jump 2 j 2500 go to 10000
Uncond. Jump (J R format) jump register 0 and 8 jr t1 go to t1
Uncond. Jump (J R format) jump and link 3 jal 2500 go to 10000 raPC4
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MIPS arithmetic instructions fyi

• Instruction Example Meaning Comments
• add add 1,2,3 1 2 3 3 operands
  exception possible
• subtract sub 1,2,3 1 2 3 3 operands
  exception possible
• add immediate addi 1,2,100 1 2 100
  constant exception possible
• add unsigned addu 1,2,3 1 2 3 3
  operands no exceptions
• subtract unsigned subu 1,2,3 1 2 3 3
  operands no exceptions
• add imm. unsign. addiu 1,2,100 1 2 100
  constant no exceptions
• multiply mult 2,3 Hi, Lo 2 x 3 64-bit
  signed product
• multiply unsigned multu2,3 Hi, Lo 2 x
  3 64-bit unsigned product
• divide div 2,3 Lo 2 3, Lo quotient, Hi
  remainder
• Hi 2 mod 3
• divide unsigned divu 2,3 Lo 2
  3, Unsigned quotient remainder
• Hi 2 mod 3
• Move from Hi mfhi 1 1 Hi Used to get copy of
  Hi
• Move from Lo mflo 1 1 Lo Used to get copy of
  Lo

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MIPS logical instructions

• Instruction Example Meaning Comment
• and and 1,2,3 1 2 3 3 reg. operands
  Logical AND
• or or 1,2,3 1 2 3 3 reg. operands
  Logical OR
• xor xor 1,2,3 1 2 Å 3 3 reg. operands
  Logical XOR
• nor nor 1,2,3 1 (2 3) 3 reg. operands
  Logical NOR
• and immediate andi 1,2,10 1 2 10 Logical
  AND reg, constant
• or immediate ori 1,2,10 1 2 10 Logical OR
  reg, constant
• xor immediate xori 1, 2,10 1 2
  10 Logical XOR reg, constant
• shift left logical sll 1,2,10 1 2 ltlt
  10 Shift left by constant
• shift right logical srl 1,2,10 1 2 gtgt
  10 Shift right by constant
• shift right arithm. sra 1,2,10 1 2 gtgt
  10 Shift right (sign extend)
• shift left logical sllv 1,2,3 1 2 ltlt 3
  Shift left by variable
• shift right logical srlv 1,2, 3 1 2 gtgt 3
  Shift right by variable
• shift right arithm. srav 1,2, 3 1 2 gtgt 3
  Shift right arith. by variable

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MIPS jump, branch, compare instructions

• Instruction Example Meaning
• branch on equal beq 1,2,25 if (1 2) go to
  PC4100 Equal test PC relative branch. Note
  Offset field 25
• branch on not eq. bne 1,2,25 if (1! 2) go to
  PC4100 Not equal test PC relative Note
  Offset field 25
• set on less than slt 1,2,3 if (2 lt 3) 11
  else 10 Compare less than 2s comp.
• set less than imm. slti 1,2,100 if (2 lt 100)
  11 else 10 Compare lt constant 2s comp.
• set less than uns. sltu 1,2,3 if (2 lt 3)
  11 else 10 Compare less than natural
  numbers
• set l. t. imm. uns. sltiu 1,2,100 if (2 lt 100)
  11 else 10 Compare lt constant natural
  numbers
• jump j 2500 go to 10000 Jump to target address
  Note jump field 2500
• jump register jr 31 go to 31 For switch,
  procedure return
• jump and link jal 2500 31 PC 4 go to
  10000 For procedure call. Note jump field
  2500