Advanced Computer Architecture 5MD00

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Advanced Computer Architecture5MD00
RISC Instruction Set Implementation
Alternatives using MIPS as example

• Nov 2013
• Henk Corporaal

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Topics

• MIPS ISA Instruction Set Architecture
• MIPS single cycle implementation
• MIPS multi-cycle implementation
• MIPS pipelined implementation
• Pipeline hazards
• Recap of RISC principles
• Other architectures
• Based on the book Computer Organization and
  Designch2-4 (3rd , 4th or 5th ed)
• Many slides I'll go quick andskip some

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Main Types of Instructions

• Arithmetic
• Integer
• Floating Point
• Memory access instructions
• Load Store
• Control flow
• Jump
• Conditional Branch
• Call Return

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MIPS arithmetic

• Most instructions have 3 operands
• Operand order is fixed (destination
  first) Example C code A B C MIPS
  code add s0, s1, s2 (s0, s1 and s2
  are associated with variables by compiler)

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MIPS arithmetic

• C code A B C D E F - A MIPS
  code add t0, s1, s2 add s0, t0,
  s3 sub s4, s5, s0
• Operands must be registers, only 32 registers
  provided
• Design Principle smaller is faster. Why?

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Registers vs. Memory

• Arithmetic instruction operands must be
  registers, only 32 registers provided
• Compiler associates variables with registers
• What about programs with lots of variables ?

Memory
CPU
register file
IO
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Register allocation

• Compiler tries to keep as many variables in
  registers as possible
• Some variables can not be allocated
• large arrays (too few registers)
• aliased variables (variables accessible through
  pointers in C)
• dynamic allocated variables
• heap
• stack
• Compiler may run out of registers gt spilling

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Memory Organization

• Viewed as a large, single-dimension array, with
  an address
• A memory address is an index into the array
• "Byte addressing" means that successive addresses
  are one byte apart

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Memory Organization

• Bytes are nice, but most data items use larger
  "words"
• For MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4

Registers hold 32 bits of data
...
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Memory layout Alignment
31
0
7
15
23
0
this word is aligned the others are not!
4
8
12
address
16
20
24

• Words are aligned
• What are the least 2 significant bits of a word
  address?

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Instructions load and store

• Example C code A8 h A8 MIPS
  code lw t0, 32(s3) add t0, s2, t0 sw
  t0, 32(s3)
• Store word operation has no destination (reg)
  operand
• Remember arithmetic operands are registers, not
  memory!

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Let's translate some C-code

• Can we figure out the code?

swap(int v, int k) int temp temp
vk vk vk1 vk1 temp
swap muli 2 , 5, 4 add 2 , 4, 2 lw
15, 0(2) lw 16, 4(2) sw 16, 0(2) sw
15, 4(2) jr 31
Explanation index k 5 base address of
v 4 address of vk is 4 4.5
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Machine Language

• Instructions, like registers and words of data,
  are also 32 bits long
• Example add t0, s1, s2
• Registers have numbers t09, s117, s218
• Instruction Format

Can you guess what the field names stand for?
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Machine Language

• Consider the load-word and store-word
  instructions,
• What would the regularity principle have us do?
• New principle Good design demands a compromise
• Introduce a new type of instruction format
• I-type for data transfer instructions
• other format was R-type for register
• Example lw t0, 32(s2) 35 18 9
  32 op rs rt 16 bit number

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Control flow

• Decision making instructions
• alter the control flow,
• i.e., change the "next" instruction to be
  executed
• MIPS conditional branch instructions bne t0,
  t1, Label beq t0, t1, Label
• Example if (ij) h i j bne s0, s1,
  Label add s3, s0, s1 Label ....

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Control flow

• MIPS unconditional branch instructions j label
• Example if (i!j) beq s4, s5, Lab1
  hij add s3, s4, s5 else j
  Lab2 hi-j Lab1 sub s3, s4,
  s5 Lab2 ...
• Can you build a simple for loop?

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So far

• Instruction Meaning
• add s1,s2,s3 s1 s2 s3sub
  s1,s2,s3 s1 s2 s3lw s1,100(s2) s1
  Memorys2100 sw s1,100(s2)
  Memorys2100 s1bne s4,s5,L Next instr.
  is at Label if s4 s5beq s4,s5,L Next
  instr. is at Label if s4 s5j Label Next
  instr. is at Label
• Formats

R I J
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Control Flow

• We have beq, bne, what about Branch-if-less-than
  ?
• New instruction meaning if s1 lt s2
  then t0 1
• slt t0, s1, s2 else t0 0
• Can use this instruction to build "blt s1, s2,
  Label" can now build general control
  structures
• Note that the assembler needs a register to do
  this, use conventions for registers

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MIPS compiler/assembler Conventions
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Constants

• Small constants are used quite frequently (50 of
  operands) e.g., A A 5 B B 1 C C -
  18
• Solutions? Why not?
• put 'typical constants' in memory and load them
• create hard-wired registers (like zero) for
  constants like 0, 1, 2,
• or .
• MIPS Instructions addi 29, 29, 4 slti 8,
  18, 10 andi 29, 29, 6 ori 29, 29, 4

3
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How about larger constants?

• We'd like to be able to load a 32 bit constant
  into a register
• Must use two instructions new "load upper
  immediate" instruction lui t0,
  1010101010101010

• Then must get the lower order bits right,
  i.e., ori t0, t0, 1010101010101010

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Assembly Language vs. Machine Language

• Assembly provides convenient symbolic
  representation
• much easier than writing down numbers
• e.g., destination first
• Machine language is the underlying reality
• e.g., destination is no longer first
• Assembly can provide 'pseudoinstructions'
• e.g., move t0, t1 exists only in Assembly
• would be implemented using add t0,t1,zero
• Another pseudo instr blt t1, t2, label
• When considering performance you should count
  real instructions

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Addresses in Branches and Jumps

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4 ? t5
• beq t4,t5,Label Next instruction is at Label
  if t4 t5
• j Label Next instruction is at Label
• Formats
• Addresses are not 32 bits How do we handle
  this with load and store instructions?

op rs rt 16 bit address
I J
op 26 bit address
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What's the next address?

• Instructions
• bne t4,t5,Label Next instruction is at Label if
  t4 ? t5
• beq t4,t5,Label Next instruction is at Label if
  t4 t5
• Formats
• Could specify a register (like lw and sw) and add
  it to address
• use Instruction Address Register (PC program
  counter)
• most branches are local (principle of locality)
• Jump instructions just use high order bits of PC
  
• address boundaries of 256 MB

op rs rt 16 bit address
I
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To summarize
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MIPS (32) addressing modes overview
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MIPS Datapath

• Building a datapath
• support a subset of the MIPS-I instruction-set
• A single cycle processor datapath
• all instruction actions in one (long) cycle
• A multi-cycle processor datapath
• each instructions takes multiple (shorter) cycles
• For details see book (ch 5, 3rd ed. Orch 4 in
  4th ed. app B)

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Datapath and Control
Registers Memories
FSM or Micro- programming
Multiplexors
Buses
ALUs
Datapath
Control
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The Processor Datapath Control

• Simplified MIPS implementation to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq, j
• Generic Implementation
• use the program counter (PC) to supply
  instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the
  registers Why?
• memory-reference?
• arithmetic?
• control flow?

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More Implementation Details

• Abstract / Simplified View
• Two types of functional units
• elements that operate on data values
  (combinational)
• elements that contain state (sequential)

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State Elements

• Unclocked vs. Clocked
• Clocks used in synchronous logic
• when should an element that contains state be
  updated?

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An unclocked state element

• The set-reset (SR) latch
• output depends on present inputs and also on past
  inputs

R
NOR
Q
NOR
Q
S
R S Q 0 0 Q 0 1 1 1 0 0 1 1 ?
Truth table
state change
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Latches and Flip-flops

• Output is equal to the stored value inside the
  element(don't need to ask for permission to look
  at the value)
• Change of state (value) is based on the clock
• Latches whenever the inputs change, and the
  clock is asserted- level sensitive
• Flip-flop state changes only on a clock edge-
  edge-triggered

A clocking methodology defines when signals can
be read and written wouldn't want to read a
signal at the same time it was being written
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D-latch (level-sensitive)

• Two inputs
• the data value to be stored (D)
• the clock signal (C) indicating when to read
  store data (D)
• Two outputs
• the value of the internal state (Q) and it's
  complement

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D flip-flop (edge-triggered)

• Output changes only on the clock edge

Q
Q
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Our Implementation

• An edge triggered methodology
• Typical execution
• read contents of some state elements,
• send values through some combinational logic,
• write results to one or more state elements

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Register File

• 3-ported one write, two read ports

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Register file read ports

• Register file built using D flip-flops

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Register file write port

• Note we still use the real clock to determine
  when to write

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Building the Datapath

• Use multiplexors to stitch them together

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Our Simple Control Structure

• All of the logic is combinational
• We wait for everything to settle down, and the
  right thing to be done
• ALU might not produce right answer right away
• we use write signals along with clock to
  determine when to write
• Cycle time determined by length of the longest
  path

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We are ignoring some details like setup and hold
times !
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Control

• Selecting the operations to perform (ALU,
  read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the
  instruction
• Exampleadd 8, 17, 18 Instruction
  Format 000000 10001 10010 01000
  00000 100000 op rs rt rd
  shamt funct
• ALU's operation based on instruction type and
  function code

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Control 2 level implementation
bit
31
6
Opcode
2
26
ALUop
instruction register
3
ALUcontrol
5
6
Funct.
0
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Datapath with Control

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ALU Control1

• What should the ALU do with this
  instructionexample lw 1, 100(2) 35
  2 1 100 op rs rt
  16 bit offset
• ALU control input 000 AND 001 OR 010 add 110
  subtract 111 set-on-less-than
• Why is the code for subtract 110 and not 011?

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ALU Control1

• Must describe hardware to compute 3-bit ALU
  control input
• given instruction type 00 lw, sw 01 beq,
  10 arithmetic
• function code for arithmetic
• Describe it using a truth table (can turn into
  gates)

inputs
outputs
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ALU Control1

• Simple combinational logic (truth tables)

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Deriving Control2 signals
9 control (output) signals
Input 6-bits
Determine these control signals directly from the
opcodesR-format 0 lw 35 sw
43 beq 4
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Control 2

• PLA example implementation

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Single Cycle Implementation

• Calculate cycle time assuming negligible delays
  except
• memory (2ns), ALU and adders (2ns), register file
  access (1ns)

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Single Cycle Implementation

• Memory (2ns), ALU adders (2ns), reg. file
  access (1ns)
• Fixed length clock longest instruction is the
  lw which requires 8 ns
• Variable clock length (not realistic, just as
  exercise)
• R-instr 6 ns
• Load 8 ns
• Store 7 ns
• Branch 5 ns
• Jump 2 ns
• Average depends on instruction mix

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Where we are headed

• Single Cycle Problems
• what if we had a more complicated instruction
  like floating point?
• wasteful of area NO Sharing of Hardware
  resources
• One Solution
• use a smaller cycle time
• have different instructions take different
  numbers of cycles
• a multicycle datapath

IR
MDR
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Multicycle Approach

• We will be reusing functional units
• ALU used to compute address and to increment PC
• Memory used for instruction and data
• Add registers after every major functional unit
• Our control signals will not be determined solely
  by instruction
• e.g., what should the ALU do for a subtract
  instruction?
• Well use a finite state machine (FSM) or
  microcode for control

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Review finite state machines

• Finite state machines
• a set of states and
• next state function (determined by current state
  and the input)
• output function (determined by current state and
  possibly input)
• Well use a Moore machine (output based only on
  current state)

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Multicycle Approach

• Break up the instructions into steps, each step
  takes a cycle
• balance the amount of work to be done
• restrict each cycle to use only one major
  functional unit
• At the end of a cycle
• store values for use in later cycles (easiest
  thing to do)
• introduce additional internal registers
• Notice we distinguish
• processor state programmer visible registers
• internal state programmer invisible registers
  (like IR, MDR, A, B, and ALUout)

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Multicycle Approach
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Multicycle Approach

• Note that previous picture does not include
• branch support
• jump support
• Control lines and logic
• Tclock gt max (ALU delay, Memory access, Regfile
  access)
• See book for complete picture

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Five Execution Steps

1. Instruction Fetch
2. Instruction Decode and Register Fetch
3. Execution, Memory Address Computation, or Branch
   Completion
4. Memory Access or R-type instruction completion
5. Write-back step

INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
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Step 1 Instruction Fetch

• Use PC to get instruction and put it in the
  Instruction Register
• Increment the PC by 4 and put the result back in
  the PC
• Can be described succinctly using RTL
  "Register-Transfer Language" IR
  MemoryPC PC PC 4
• Can we figure out the values of the control
  signals?
• What is the advantage of updating the PC now?

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Step 2 Instruction Decode and
Register Fetch

• Read registers rs and rt in case we need them
• Compute the branch address in case the
  instruction is a branch
• Previous two actions are done optimistically!!
• RTL A RegIR25-21 B RegIR20-16
  ALUOut PC(sign-extend(IR15-0)ltlt 2)
• We aren't setting any control lines based on the
  instruction type (we are busy "decoding" it in
  our control logic)

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Step 3 (instruction dependent)

• ALU is performing one of four functions, based on
  instruction type
• Memory Reference ALUOut A
  sign-extend(IR15-0)
• R-type ALUOut A op B
• Branch if (AB) PC ALUOut
• Jump
• PC PC31-28 (IR25-0ltlt2)

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Step 4 (R-type or Memory-access)

• Loads and stores access memory MDR
  MemoryALUOut or MemoryALUOut B
• R-type instructions finish RegIR15-11
  ALUOutThe write actually takes place at the
  end of the cycle on the edge

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Write-back step

• Memory read completion step RegIR20-16
  MDR
• What about all the other instructions?

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Summary execution steps
Steps taken to execute any instruction class
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Simple Questions

• How many cycles will it take to execute this
  code? lw t2, 0(t3) lw t3, 4(t3) beq t2,
  t3, L1 assume not taken add t5, t2,
  t3 sw t5, 8(t3)L1 ...
• What is going on during the 8th cycle of
  execution?
• In what cycle does the actual addition of t2 and
  t3 takes place?

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Implementing the Control

• Value of control signals is dependent upon
• what instruction is being executed
• which step is being performed
• Use the information we have accumulated to
  specify a finite state machine (FSM)
• specify the finite state machine graphically, or
• use microprogramming
• Implementation can be derived from specification

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Graphical Specification of FSM

• How many state bits will we need?

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Finite State Machine for Control

• Implementation

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PLA Implemen-tation
opcode
(see book)
current state

• If I picked a horizontal or vertical line could
  you explain it ?
• What type of FSM is used?Mealy or Moore?

datapath control
next state
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Pipelined implementation

• Pipelining
• Pipelined datapath
• Pipelined control
• Hazards
• Structural
• Data
• Control
• Exceptions
• Scheduling
• For details see the book (chapter 6)

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Pipelining

• Improve performance by increasing instruction
  throughput

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Pipelining

• Ideal speedup number of stages
• Do we achieve this?

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Pipelining

• What makes it easy
• all instructions are the same length
• just a few instruction formats
• memory operands appear only in loads and stores
• What makes it hard?
• structural hazards suppose we had only one
  memory
• control hazards need to worry about branch
  instructions
• data hazards an instruction depends on a
  previous instruction
• Well build a simple pipeline and look at these
  issues
• Well talk about modern processors and what
  really makes it hard
• exception handling
• trying to improve performance with out-of-order
  execution, etc.

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Basic idea start from single cycle impl.

• What do we need to add to actually split the
  datapath into stages?

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Pipelined Datapath

• Can you find a problem even if there are no
  dependencies? What instructions can we execute
  to manifest the problem?

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Corrected Datapath
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Graphically Representing Pipelines

• Can help with answering questions like
• how many cycles does it take to execute this
  code?
• what is the ALU doing during cycle 4?
• use this representation to help understand
  datapaths

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Pipeline Control
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Pipeline control

• We have 5 stages. What needs to be controlled in
  each stage?
• Instruction Fetch and PC Increment
• Instruction Decode / Register Fetch
• Execution
• Memory Stage
• Write Back
• How would control be handled in an automobile
  plant?
• a fancy control center telling everyone what to
  do?
• should we use a finite state machine?

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Pipeline Control
(compare single cycle control!)

• Pass control signals along
• just like the data

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Datapath with Control
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Hazards
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Hazards problems due to pipelining

• Three Hazard types
• Structural
• same resource is needed multiple times in the
  same cycle
• Data
• data dependencies limit pipelining
• Control
• next executed instruction may not be the next
  specified instruction

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Structural hazards

• Examples
• Two accesses to a single ported memory
• Two operations need the same function unitat the
  same time
• Two operations need the same function unitin
  successive cycles, but the unit is not pipelined
• Solutions
• stalling
• add more hardware

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Structural hazards on MIPS

• Q Do we have structural hazards on our simple
  MIPS pipeline?

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Data hazards

• Data dependencies
• RaW (read-after-write)
• WaW (write-after-write)
• WaR (write-after-read)
• Hardware solution
• Forwarding / Bypassing
• Detection logic
• Stalling
• Software solution Scheduling

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Data dependences

• Three types RaW, WaR and WaW
• add r1, r2, 5 r1 r25
• sub r4, r1, r3 RaW of r1
• add r1, r2, 5
• sub r2, r4, 1 WaR of r2
• add r1, r2, 5
• sub r1, r1, 1 WaW of r1
• st r1, 5(r2) Mr25 r1
• ld r5, 0(r4) RaW if 5r2 0r4

WaW and WaR do not occur in simple pipelines, but
they limit scheduling freedom! Problems for
your compiler and Pentium! ? use register
renaming to solve this!
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RaW on MIPS pipeline
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Forwarding

• Use temporary results, dont wait for them to be
  written
• register file forwarding to handle read/write to
  same register
• ALU forwarding

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Forwarding hardware
ALU forwarding circuitry principle

• Note there are two options
• buf - ALU bypass mux - buf
• buf - bypass mux ALU - buf

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Forwarding
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Forwarding check

• Check for matching register-ids
• For each source-id of operation in the EX-stage
  check if there is a matching pending dest-id

Q. How many comparators do we need?
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Can't always forward

• Load word can still cause a hazard
• an instruction tries to read register r following
  a load to the same r
• Need a hazard detection unit to stall the load
  instruction

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Stalling

• We can stall the pipeline by keeping an
  instruction in the same stage

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Hazard Detection Unit
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96
Software only solution?

• Have compiler guarantee that no hazards occur
• Example where do we insert the NOPs
  ? sub 2, 1, 3 and 12, 2, 5 or 13,
  6, 2 add 14, 2, 2 sw 13, 100(2)
• Problem this really slows us down!

sub 2, 1, 3 nop nopand 12, 2, 5or 13,
6, 2add 14, 2, 2 nopsw 13, 100(2)
97
Control hazards

• Control operations may change the sequential flow
  of instructions
• branch
• jump
• call (jump and link)
• return
• (exception/interrupt and rti / return from
  interrupt)

98
Control hazard Branch

• Branch actions
• Compute new address
• Determine condition
• Perform the actual branch (if taken) PC new
  address

99
Branch example
100
Branching

• Squash pipeline
• When we decide to branch, other instructions are
  in the pipeline!
• We are predicting branch not taken
• need to add hardware for flushing instructions if
  we are wrong

101
Branch with predict not taken
Clock cycles
Branch L
IF
ID
EX
MEM
WB
Predict not taken
IF
ID
EX
MEM
WB
IF
ID
EX
MEM
WB
L
102
Branch speedup

• Earlier address computation
• Earlier condition calculation
• Put both in the ID pipeline stage
• adder
• comparator

103
Improved branching / flushing IF/ID

104
Exception support

• Types of exceptions
• Overflow
• I/O device request
• Operating system call
• Undefined instruction
• Hardware malfunction
• Page fault
• Precise exception
• finish previous instructions (which are still in
  the pipeline)
• flush excepting and following instructions, redo
  them after handling the exception(s)

105
Exceptions

• Changes needed for handling overflow exception of
  an operation in EX stage (see book for details)
• Extend PC input mux with extra entry with fixed
  address
• Add EPC register recording the ID/EX stage PC
• this is the address of the next instruction !
• Cause register recording exception type
• E.g., in case of overflow exception insert 3
  bubblesflush the following stages
• IF/ID stage
• ID/EX stage
• EX/MEM stage

106
Scheduling, why?

• Lets look at the execution time
• Texecution Ncycles x Tcycle
• Ninstructions x CPI x Tcycle
• Scheduling may reduce Texecution
• Reduce CPI (cycles per instruction)
• early scheduling of long latency operations
• avoid pipeline stalls due to structural, data and
  control hazards
• allow Nissue gt 1 and therefore CPI lt 1
• Reduce Ninstructions
• compact many operations into each instruction
  (VLIW)

107
Scheduling data hazardsexample 1

• Try and avoid RaW stalls (in this case load
  interlocks)!
• E.g., reorder these instructions

lw t0, 0(t1) lw t2, 4(t1) sw t0, 4(t1) sw
t2, 0(t1)
lw t0, 0(t1) lw t2, 4(t1) sw t2, 0(t1) sw
t0, 4(t1)
?
108
Scheduling data hazardsexample 2
Avoiding RaW stalls
Reordering instructions for following program (by
you or the compiler)
Code a b c d e - f
109
Scheduling control hazards

• Texecution Ninstructions x CPI x Tcycle
• CPI CPIideal fbranch x Pbranch
• Pbranch Ndelayslots x miss_rate
• Modern processors tend to have large branch
  penalty, Pbranch, due to
• many pipeline stages
• multi-issue
• Note that penalties have larger effect when
  CPIideal is low

110
Scheduling control hazards

• What can we do about control hazards and CPI
  penalty?
• Make penalty Pbranch low
• Early computation of new PC
• Early determination of condition
• Visible branch delay slots filled by compiler
  (MIPS)
• Branch prediction
• Reduce control dependencies (control height
  reduction) Schlansker and Kathail, Micro95
• Remove branches if-conversion
• Conditional instructions CMOVE, cond skip next
• Guarding all instructions TriMedia

111
Branch delay slot

• Add a branch delay slot
• the next instruction after a branch is always
  executed
• rely on compiler to fill the slot with
  something useful
• Is this a good idea?
• let's look how it works

112
Branch delay slot scheduling
Q. What to put in the delay slot?
op 1
beq r1,r2, L
.............
op 2
.............
'fall-through'
L op 3
branch target
.............
113
Summary

• Modern processors are (deeply) pipelined, to
  reduce Tcycle and aim at CPI 1
• Hazards increase CPI
• Several software and hardware measures to avoid
  or reduce hazards are taken
• Not / partly discussed, but important
  developments
• Multi-issue further reduces CPI
• Branch prediction to avoid high branch penalties
• Dynamic scheduling
• In all cases a scheduling compiler needed

114
Recap of MIPS

• RISC architecture
• Register space
• Addressing
• Instruction format
• Pipelining

115
Why RISC? Keep it simple

• RISC characteristics
• Reduced number of instructions
• Limited addressing modes
• load-store architecture
• enables pipelining
• Large register set
• uniform (no distinction between e.g. address and
  data registers)
• Limited number of instruction sizes (preferably
  one)
• know directly where the following instruction
  starts
• Limited number of instruction formats
• Memory alignment restrictions
• ......
• Based on quantitative analysis
• " the famous MIPS one percent rule" don't even
  think about it when its not used more than one
  percent

116
Register space
32 integer (and 32 floating point) registers of
32-bit
117
Addressing
118
Instruction format
R I J
Example instructions Instruction
Meaning add s1,s2,s3 s1 s2 s3
addi s2,s3,4 s2 s3 4 lw
s1,100(s2) s1 Memorys2100 bne
s4,s5,L if s4ltgts5 goto L j Label
goto Label
119
Pipelining
All integer instructions fit into the following
pipeline
120
Other architecture styles

• Accumulator architecture
• one operand (in register or memory), accumulator
  almost always implicitly used
• Stack
• zero operand all operands implicit (on TOS)
• Register (load store)
• three operands, all in registers
• loads and stores are the only instructions
  accessing memory (i.e. with a memory (indirect)
  addressing mode
• Register-Memory
• two operands, one in memory
• Memory-Memory
• three operands, may be all in memory
• (there are more varieties / combinations)

121
Accumulator architecture
Example code a bc load b //
accumulator is implicit operand add c store a
122
Stack architecture
latch
latch
top of stack
ALU
Memory
stack pt
latch
Example code a bc push b push c add pop
a
123
Other architecture styles
Let's look at the code for C A B
Stack Architecture Accumulator Architecture Register-Memory Memory-Memory Register (load-store)
Push A Load A Load r1,A Add C,B,A Load r1,A
Push B Add B Add r1,B Load r2,B
Add Store C Store C,r1 Add r3,r1,r2
Pop C Store C,r3
Q What are the advantages / disadvantages of
load-store (RISC) architecture?