Introduction%20to%20VHDL - PowerPoint PPT Presentation

About This Presentation
Title:

Introduction%20to%20VHDL

Description:

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed ... – PowerPoint PPT presentation

Number of Views:206
Avg rating:3.0/5.0
Slides: 19
Provided by: Debbie360
Category:

less

Transcript and Presenter's Notes

Title: Introduction%20to%20VHDL


1
Introduction to VHDL
  • VHDL Tutorial
  • R. E. Haskell and D. M. Hanna
  • T1 Combinational Logic Circuits

2
Introduction to VHDL
  • VHDL is an acronym for VHSIC (Very High Speed
    Integrated Circuit) Hardware Description Language
  • IEEE standard specification language (IEEE
    1076-1993) for describing digital hardware used
    by industry worldwide
  • VHDL enables hardware modeling from the gate
    level to the system level

3
Combinational Circuit Example
8-line 2-to-1 Multiplexer
8-line 2 x 1 MUX
a(70)
y(70)
b(70)
sel y 0 a 1 b
sel
4
An 8-line 2 x 1 MUX
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
5
Entity
Each entity must begin with these library and use
statements
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
port statement defines inputs and outputs
6
Entity
Mode in or out
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
Data type STD_LOGIC, STD_LOGIC_VECTOR(7 downto
0)
7
Standard Logic
library IEEE use IEEE.std_logic_1164.all
type std_ulogic is ( U, -- Uninitialized X
-- Forcing unknown 0 -- Forcing
zero 1 -- Forcing one Z -- High
impedance W -- Weak unknown L --
Weak zero H -- Weak one -) --
Dont care
8
Standard Logic
Type std_ulogic is unresolved. Resolved signals
provide a mechanism for handling the problem of
multiple output signals connected to one
signal. subtype std_logic is resolved
std_ulogic
9
Architecture
  architecture mux2_arch of mux2 is begin
mux2_1 process(a, b, sel) begin if sel
'0' then y lt a else y
lt b end if end process mux2_1 end
mux2_arch
Note lt is signal assignment
10
Architecture
entity name
process sensitivity list
  architecture mux2_arch of mux2 is begin
mux2_1 process(a, b, sel) begin if sel
'0' then y lt a else y
lt b end if end process mux2_1 end
mux2_arch
Sequential statements (ifthenelse) must be in a
process
Note beginend in process
Note beginend in architecture
11
(No Transcript)
12
(No Transcript)
13
An 8-line 4 x 1 multiplexer
a(70)
8-line
b(70)
4 x 1
y(70)
c(70)
MUX
d(70)
sel(10)
14
An 8-line 4 x 1 multiplexer
library IEEE use IEEE.std_logic_1164.all   entit
y mux4 is port ( a in
STD_LOGIC_VECTOR (7 downto 0) b in
STD_LOGIC_VECTOR (7 downto 0) c in
STD_LOGIC_VECTOR (7 downto 0) d in
STD_LOGIC_VECTOR (7 downto 0) sel in
STD_LOGIC_VECTOR (1 downto 0) y out
STD_LOGIC_VECTOR (7 downto 0) ) end mux4
15
Example of case statement
architecture mux4_arch of mux4 is begin process
(sel, a, b, c, d) begin case sel is
when "00" gt y lt a when "01" gt y lt
b when "10" gt y lt c when others
gt y lt d end case end process end
mux4_arch
Note implies operator gt
Must include ALL posibilities in case statement
16
VHDL Architecture Structure
architecture name_arch of name is begin
end name_arch
Signal assignments
Processes contain sequential statements, but
execute concurrently within the architecture body

Concurrent statements
Process 1
Concurrent statements
Process 2
Concurrent statements
17
VHDL Process
P1 process (ltsensitivity list) ltvariable
declarationsgt begin ltsequential
statementsgt end process P1
Within a process Variables are assigned using
and are updated immediately. Signals are
assigned using lt and are updated at the end
of the process.
18
Lab Exercise T1
  • Multiplexer Simulation
  • using Aldec Active-HDL
Write a Comment
User Comments (0)
About PowerShow.com