Implementation%20of%20a%20noise%20subtraction%20algorithm%20using%20Verilog%20HDL

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Implementation of a noise subtractionalgorithm
using Verilog HDL University of Massachusetts,
Amherst Department of Electrical Computer
Engineering, Course 559/659 by Perry Levy, Aseem
Pangotra, Stephan Stiglmayr and Thomas
Kunkel Team Leader Prof. Maciej Ciesielski
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Noise-subtracting algorithm

• Time to frequency transformation
• Subtraction of magnitudes
• Distortion correction
• Frequency to time transformation

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm

• Serial data
• Shifts of 16bits
• Storing in 1032 x 32bit memory
• Flushing memory to FFT after receiving of 256
  pairs of data

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
State machine
Algorithm
Flushing memory
storing data in memory
Reset
256 pairs
Modules
Buffer emptied
In- / Output
Emptying buffer
Buffering data
Mem flushed
FFT
Subtraction
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Noise-subtracting algorithm
Block Diagram
Address
Address generator
Data
WR RD
Algorithm
SCLK
Flushing
Valid
Real part
Serial shifter
LRCLK
Output
Modules
Imaginary
1024 x 32bit RAM
Reset
Data
Data
Buffer
Enable
Done
In- / Output
Hold
FFT
16bit counter
Finite state machine
Subtraction
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Noise-subtracting algorithm

• Parallel input and output of variables
• 16Bit address, 8Bit data (compatible to
  microcontroller)
• Preset values when resetting

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm

• Implementation of Radix 2 algorithm
• Window length 1024
• 16Bit fixed point arithmetics
• 2 FFTs at the same time by using real and
  imaginary signal
• Reconstruction afterwards needed

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm

• Butterfly structure as fundamental cell

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Signal-flow Graph for 8 point FFT
f(0)
F(0)
Algorithm
F(1)
-1
W0
F(2)
-1
Modules
W2
F(3)
-1
-1
In- / Output
W0
F(4)
-1
FFT
W1
F(5)
-1
-1
W0
W2
Subtraction
F(6)
-1
-1
W2
W3
f(7)
F(7)
-1
-1
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Noise-subtracting algorithm

• Sequential implementation
• 1Bit shiftdown after each step to prevent
  overflow
• RAM 1024 x 32Bit
• Controller (Finite state machine)
• Address generator
• Coefficient ROM

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Block Diagram
input_ready
output_ready
Algorithm
bus_select
Controller
Modules
write_en
RAM
read_en
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32
Data In
In- / Output
Data
input_mode
io_mode
fft_mode
fft_done
io_done
Bus
ram_addr1
ram_addr2
Butterfly
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32
32
FFT
Processor
Data Out
Address Generator
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twiddle
Subtraction
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Coeff. ROM
FFT PROCESSOR
rom_addr
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Noise-subtracting algorithm
Delay estimation

• Input 512
• FFT processing 251210
• output 512
• Sum 11264 clock cycles

Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Simulations
Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Spectra reconstruction
Algorithm
Re
Im
Modules
Re
Im
In- / Output
Re
Im
FFT
Subtraction
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Noise-subtracting algorithm
Error compared to 32bit floating point
Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Error compared to 32bit floating point
Algorithm
Modules
In- / Output
FFT
Subtraction
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Noise-subtracting algorithm
Error compared to 32bit floating point
Algorithm
Modules
In- / Output
FFT
Subtraction
(absolute values plotted)
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C.O.R.D.I.C

• An acroynm for
• Coordinate Rotation DIgital Computer

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CORDIC? WHY USE IT?

• CORDIC was derived by Volder in the 50s to
  calculate trigonometric function.
• CORDIC can also calculate hyperbolic, linear and
  logarithmic functions.
• CORDIC processing offers high computational rates
  ? fast enough for demanding DSP tasks.
• Hardware-efficient algorithm, requires only
  shifts and adds.

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THE CORDIC ALGORITHM

• Provides an iterative method of performing vector
  rotations by arbitrary angles using only shifts
  and adds.
• Multiplication by tangent term can be avoided if
  the rotation angles are restricted to
  tan(?)2-i.
• In digital hardware simple shift operation.

The individual equations can be rewritten
rearranged so that
The basic CORDIC-equations for rotation and
vectoring mode
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Vectoring and Rotation Modes

• Rotation mode performs Polar to Cartesian
  transformation by rotating the input vector by a
  specified angle (given as an argument).

• Vectoring mode performs Cartesian to Polar
  transformation by rotating input vector to the
  x-axis while recording the angle required to make
  that rotation.

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Word-Parallel Pipelined CORDIC

• CORDIC Processor core built around three
  fundamental modules
• Pre-Processor manipulates inputs to fit in -1 to
  1 rad. so that the algorithm covers entire 2?
  range.
• CORDIC core performs actual algorithm in
  parallel using a pipeline of CordicPipe blocks.
• Post-Processor places results in correct
  quadrant.

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RECTANGULAR TO POLAR CONVERSION

• Takes two 16-bit signed words as inputs (Xin,Yin)
• CORDIC core returns equivalent polar coordinates
  where Rout is the magnitude and Aout is the
  angle.
• Outputs are in fractional format with the upper
  16-bits represent decimal value and lower 4-bits
  represent fractional value.

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POLAR TO RECTANGULAR CONVERSION

• Takes 16-bit magnitude from subtraction and
  stored angle as inputs (Rin, Ain).
• CORDIC core returns equivalent rectangular
  coordinates Xo and Yo.
• Core only converges in the range -90 to 90
  degrees, must write a pre and post processor so
  that algorithm covers entire 2? range.

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FUTURE WORK

• Need to write test bench for rect2polar and
  polar2rect modules.
• Need to finish writing pre and post processor for
  polar2rect module.
• Need to connect my modules to my partners
  modules.
• Need to test and verify that they work well
  together.

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Noise-subtracting algorithm
Block diagram
Beta
Algorithm
16
Modules
1 if xgty, else 0
a
x
Comp
In- / Output
sel
b
FFT
Sub
Subtraction
Alpha
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Noise-subtracting algorithm

• Inputs two, 16 unsigned bits each
• ( A and B)
• Multiplication Alpha and Beta terms
• Subtraction ((original A)-(AlphaB))
• Comparators (A gt B) out 1, else out 0
• Multiplexer
• (Inputs Select, ABeta, subtractor output)
• Select 1, final_out x
• Select 0, final_out y

Algorithm
Modules
In- / Output
FFT
Subtraction
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FUTURE WORK

• Connect all modules together.
• Need to write and verify RTL code.
• Synthesize all code and implement in FPGA.
• Test FPGA.