FPGAs and VHDL

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FPGAs and VHDL

• Lecture L12.1

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FPGAs and VHDL

• Field Programmable Gate Arrays (FPGAs)
• VHDL
• 2 x 1 MUX
• 4 x 1 MUX
• An Adder
• Binary-to-BCD Converter
• A Register
• Fibonacci Sequence Generator

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Block diagram of Xilinx Spartan IIE FPGA
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Each Spartan IIE CLB contains two of these CLB
slices
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Look Up Tables

• Combinatorial Logic is stored in 16x1 SRAM Look
  Up Tables (LUTs) in a CLB
• Example

Look Up Table
4-bit address
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(2 )
2
64K !

• Capacity is limited by number of inputs, not
  complexity
• Choose to use each function generator as 4 input
  logic (LUT) or as high speed sync.dual port RAM

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Introduction to VHDL

• VHDL is an acronym for VHSIC (Very High Speed
  Integrated Circuit) Hardware Description Language
• IEEE standard specification language (IEEE
  1076-1993) for describing digital hardware used
  by industry worldwide
• VHDL enables hardware modeling from the gate
  level to the system level

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Combinational Circuit Example
8-line 2-to-1 Multiplexer
8-line 2 x 1 MUX
a(70)
y(70)
b(70)
sel y 0 a 1 b
sel
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An 8-line 2 x 1 MUX
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
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Entity
Each entity must begin with these library and use
statements
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
port statement defines inputs and outputs
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Entity
Mode in or out
library IEEE use IEEE.std_logic_1164.all   entit
y mux2 is port ( a in
STD_LOGIC_VECTOR(7 downto 0) b in
STD_LOGIC_VECTOR(7 downto 0) sel in
STD_LOGIC y out STD_LOGIC_VECTOR(7
downto 0) ) end mux2
Data type STD_LOGIC, STD_LOGIC_VECTOR(7 downto
0)
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Architecture
  architecture mux2_arch of mux2 is begin
mux2_1 process(a, b, sel) begin if sel
'0' then y lt a else y
lt b end if end process mux2_1 end
mux2_arch
Note lt is signal assignment
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Architecture
entity name
process sensitivity list
  architecture mux2_arch of mux2 is begin
mux2_1 process(a, b, sel) begin if sel
'0' then y lt a else y
lt b end if end process mux2_1 end
mux2_arch
Sequential statements (ifthenelse) must be in a
process
Note beginend in process
Note beginend in architecture
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An 8-line 4 x 1 multiplexer
a(70)
8-line
b(70)
4 x 1
y(70)
c(70)
MUX
d(70)
sel(10)
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An 8-line 4 x 1 multiplexer
library IEEE use IEEE.std_logic_1164.all   entit
y mux4 is port ( a in
STD_LOGIC_VECTOR (7 downto 0) b in
STD_LOGIC_VECTOR (7 downto 0) c in
STD_LOGIC_VECTOR (7 downto 0) d in
STD_LOGIC_VECTOR (7 downto 0) sel in
STD_LOGIC_VECTOR (1 downto 0) y out
STD_LOGIC_VECTOR (7 downto 0) ) end mux4
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Example of case statement
architecture mux4_arch of mux4 is begin process
(sel, a, b, c, d) begin case sel is
when "00" gt y lt a when "01" gt y lt
b when "10" gt y lt c when others
gt y lt d end case end process end
mux4_arch
Note implies operator gt
Must include ALL posibilities in case statement
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An Adder
-- Title adder library IEEE use
IEEE.std_logic_1164.all use IEEE.std_logic_unsign
ed.all   entity adder is generic(widthpositi
ve) port ( a in STD_LOGIC_VECTOR(width-1
downto 0) b in STD_LOGIC_VECTOR(width-1
downto 0) y out STD_LOGIC_VECTOR(width-
1 downto 0) ) end adder   architecture
adder_arch of adder is begin add1 process(a,
b) begin y lt a b end process
add1 end adder_arch
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Binary-to-BCD Converter
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-- Title Binary-to-BCD Converter library
IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_unsigned.all   entity binbcd is
port ( B in STD_LOGIC_VECTOR (7 downto
0) P out STD_LOGIC_VECTOR (9 downto 0)
) end binbcd
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architecture binbcd_arch of binbcd is begin
bcd1 process(B) variable z
STD_LOGIC_VECTOR (17 downto 0) begin
for i in 0 to 17 loop z(i) '0' end
loop z(10 downto 3) B   for i in 0
to 4 loop if z(11 downto 8) gt 4 then
z(11 downto 8) z(11 downto 8) 3 end
if if z(15 downto 12) gt 4 then z(15
downto 12) z(15 downto 12) 3 end if
z(17 downto 1) z(16 downto 0) end
loop P lt z(17 downto 8) end
process bcd1 end binbcd_arch
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A Register
-- A width-bit register library IEEE use
IEEE.std_logic_1164.all   entity reg is
generic(width positive) port ( d
in STD_LOGIC_VECTOR (width-1 downto 0)
load in STD_LOGIC clr in
STD_LOGIC clk in STD_LOGIC q
out STD_LOGIC_VECTOR (width-1 downto 0)
) end reg  
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Register architecture
architecture reg_arch of reg is begin
process(clk, clr) begin if clr '1' then
for i in width-1 downto 0 loop q(i)
lt '0' end loop elsif (clk'event and
clk '1') then if load '1' then
q lt d end if end if end process
end reg_arch
Infers a flip-flop for all outputs (q)
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Fibonacci Sequence
-- Title Fibonacci Sequence library IEEE use
IEEE.STD_LOGIC_1164.all use IEEE.std_logic_unsign
ed.all   entity fib is port( clr in
std_logic clk in std_logic P out
std_logic_vector(9 downto 0) ) end fib
P
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architecture fib_arch of fib is   component
adder generic( width POSITIVE) port( a
in std_logic_vector((width-1) downto 0) b in
std_logic_vector((width-1) downto 0) y out
std_logic_vector((width-1) downto 0)) end
component   component reg generic( width
POSITIVE) port( d in std_logic_vector((width
-1) downto 0) load in std_logic clr in
std_logic set in std_logic clk in
std_logic q out std_logic_vector((width-1)
downto 0)) end component
Declare components
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component binbcd port( B in
std_logic_vector(7 downto 0) P out
std_logic_vector(9 downto 0)) end
component   signal r, s, t std_logic_vector(7
downto 0) signal one, zero std_logic constant
bus_width positive 8
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begin one lt '1' zero lt '0'   U1
adder generic map(width gt bus_width) port map
(a gt t, b gt r, y gt s) R1 reg generic
map(width gt bus_width) port map (d gt r, load
gtone, clr gt zero, set gt clr, clk gtclk, q
gt t) W reg generic map(width gt
bus_width) port map (d gt s, load gt one, clr
gt clr, set gt zero, clk gtclk, q gt r)  
U2 binbcd port map (B gt r, P gt P) end
fib_arch
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Fibonacci Sequence Works!