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PROGRAMMABLE LOGIC DESIGN WITH VHDL

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Allows designers to quickly develop designs requiring tens of thousands of logic ... Commercial Sim and Synthesis tools become available and 1164 pkg enables ... – PowerPoint PPT presentation

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Title: PROGRAMMABLE LOGIC DESIGN WITH VHDL


1
PROGRAMMABLE LOGIC DESIGN WITH VHDL
2
Objectives
  • Upon completion of this training, your VHDL
    knowledge will enable you to
  • Implement efficient combinatorial and sequential
    logic
  • Design state machines and understand
    implementation trade-offs
  • Use hierarchy / Create reusable components
  • Identify how VHDL will synthesize and fit into a
    PLD, CPLD and FPGA

3
Objectives (contd.)
  • Upon completion of this training, you will be
    able to use Warp to
  • Compile and synthesize VHDL designs for
    programmable logic devices
  • Create VHDL or Verilog timing simulation models
    for popular third party simulators.
  • Target PLDs/CPLDs
  • Simulate the resulting device with the Aldec full
    timing simulator
  • Use the report file to determine operating
    frequency, set-up time, clock to output delay,
    and device resource usage.

4
Agenda
  • Intro, Why Use VHDL?,
  • Design Flow
  • VHDL Design Descriptions
  • The Entity, Ports, Modes, Types
  • Exercise 1 - Write an entity statement
  • The Architecture, differing styles
  • Concurrent and Sequential statements
  • Processes Signals vs. Variables
  • VHDL Operators/Overloading/Inferencing
  • VHDL Identifiers
  • Exercise 2 - write an architecture
  • Tri-State Logic, Don't Cares
  • Warp GUI overview
  • Exercise 3 - Design a bus controller
  • Aggregates and Subscripts
  • Registers, Latches and Implicit Memory
  • Exercise 4 - Design a counter
  • Lunch
  • State Machines and State Encoding
  • Exercise 5 - Design a state machine
  • Design Hierarchy - components, pkgs, libraries
  • Exercise 6 - Design a loadable counter hierarchy
  • Generate Statement
  • Multiplexing I/O pins
  • Exercise 7 - DRAM output controller
  • User defined attributes
  • CPLD synthesis directives
  • Miscellaneous Topics and Wrap-up

5
Introduction
  • VHDL is used to
  • document circuits
  • simulate circuits
  • synthesize design descriptions
  • Synthesis is the reduction of a design
    description to a lower-level representation (such
    as a netlist or a set of equations).
  • This training course covers VHDL for PLD
    synthesis
  • The course will at times draw upon the concepts
    of VHDL as a simulation language

6
Why Use VHDL?
  • Quick Time-to-Market
  • Allows designers to quickly develop designs
    requiring tens of thousands of logic gates
  • Provides powerful high-level constructs for
    describing complex logic
  • Supports modular design methodology and multiple
    levels of hierarchy
  • One language for design and simulation
  • Allows creation of device-independent designs
    that are portable to multiple vendors. Good for
    ASIC Migration
  • Allows user to pick any synthesis tool, vendor,
    or device

7
VHDL vs. Verilog History
  • Developed by DoD in early 80s as means for
    Contractors to Describe Designs-Funded VHSIC
  • 1987 IEEE ratified 1076 and DoD mandated
    VHDL(F-22) and EDA vendors created tools.
  • 1993 - IEEE 1076 93
  • 1996 Commercial Sim and Synthesis tools become
    available and 1164 pkg enables multi value logic
  • 1983 -Gateway founded by Genrads HDL and HILO
    simulator author.Releases Verilog HDL and
    Simulator
  • 1985 Enhanced Verilog-XL-used for high end
    designs -Fast Simulator - interpretive-no need to
    precompile
  • 1990 Cadence buys Gateway-nearly all ASIC
    foundries used XL as Golden Simulator
  • 1995 IEEE 1364

8
VHDL vs. VerilogCompilation/Data Types/High
Level Constructs/Verbosity/Ease
  • Many E-A pairs may reside in single system file.
  • User Can define Data Types-Powerful
  • High Level Modeling w/ Package, Config, Generate
  • Strongly Typed Language - models must be
    precisely coded-often longer code
  • Less intuitive but much more powerful constructs
  • Order or Code is crucial to obtaining desired
    output.
  • Simple Data Types are controlled by language
  • No Equivalent High Level Modeling Constructs
  • Verilog has looser structure-can lead to unwanted
    and unidentified errors-more concise code.
  • Easiest to Grasp-more prone to create unwanted
    results

9
WARP5.0
  • WARP2 Release 5.0 now supports Verilog Synthesis
  • Same great Synthesis as VHDL
  • Includes Aldec Full Timing Simulator and FSM
    Editor
  • Generates timing simulation models for major
    third party VHDL and Verilog simulators
  • New GUI-Microsoft Std Interface
  • Even Better HDL Editor
  • Supports All Cypress Devices
  • Windows 95, NT, UNIX
  • Same Great 99 Price

10
Warp2/Warp3/Programming
Design Entry
Schematic
Text/FSM
Front End
Simulation
Synthesis
Design Compilation
Back End
Design Verification
11
VHDL Design Descriptions
  • VHDL design descriptions consist of an ENTITY
    declaration and an ARCHITECTURE body
  • The ENTITY declaration describes the design I/O
  • The ARCHITECTURE body describes the content or
    function of the design
  • Every architecture needs an entity so it is
    common to refer to them together as an
    ENTITY/ARCHITECTURE PAIR

12
Example Entity/Architecture PairA 2-Input And
Function
  • ENTITY and2 IS PORT (
  • a,b IN std_logic
  • f OUT std_logic)
  • END and2
  • ARCHITECTURE behavioral OF and2 IS
  • BEGIN
  • f lt a AND b
  • END behavioral

13
The Entity
  • A BLACK BOX
  • The ENTITY describes the periphery of the black
    box (i.e., the design I/O)

BLACK_BOX
rst
q70
d70
co
clk
14
Example Entity declaration
  • ENTITY black_box IS PORT (
  • clk, rst IN std_logic
  • d IN std_logic_vector(7 DOWNTO 0)
  • q OUT std_logic_vector(7 DOWNTO 0)
  • co OUT std_logic)
  • END black_box
  • What does all this mean?

15
The Entity Declaration
  • ENTITY entity_name IS
  • -- optional generics
  • PORT (
  • name mode type
  • ...
  • )
  • END entity_name
  • entity_name is an arbitrary name
  • generics are used for defining parameterized
    components
  • name is the signal/port identifier and may be a
    comma separated list for ports of identical modes
    and types
  • mode describes the direction the data is flowing
  • type indicates the set of values name may be
    assigned


16
Ports
  • The Entity (BLACK BOX) has PORTS
  • PORTS are the points of communication
  • PORTS are usually the device pins
  • PORTS have an associated name, mode, and type

17
Port Modes
  • A ports MODE indicates the direction that data
    is transferred
  • IN Data goes into the entity only
  • OUT Data goes out of the entity only (and is
    not used internally)
  • INOUT Data is bi-directional (goes into and
    out of the entity)
  • BUFFER Data that goes out of the entity and
    is also fed-back internally

18
IEEE 1076 Types
  • VHDL is a strongly typed language (you cannot
    assign a signal of one type to the signal of
    another type)
  • bit - a signal of type bit that can only take
    values of '0' or '1'
  • bit_vector - a grouping of bits (each can be '0'
    or '1')

SIGNAL a BIT_VECTOR(0 TO 3) -- ascending
range SIGNAL b BIT_VECTOR(3 DOWNTO 0) --
descending range a lt "0111" -- double quotes
used for vectors b lt "0101" This means
that a(0) '0' b(0) '1' a(1) '1' b(1)
'0' a(2) '1' b(2) '1' a(3) '1'
b(3) '0'
19

IEEE 1076 TYPES (contd.)
  • INTEGER
  • useful as index holders for loops, constants,
    generics, or high-level modeling
  • BOOLEAN
  • can take values TRUE or FALSE
  • ENUMERATED
  • has user defined set of possible values, e.g.,
  • TYPE traffic_light IS (green, yellow, red)

20
IEEE 1164
  • A package created to solve the limitations of
    the BIT type
  • Nine values instead of just two ('0' and '1')
  • Allows increased flexibility in VHDL coding,
    synthesis, and simulation
  • STD_LOGIC and STD_LOGIC_VECTOR are used instead
    of BIT and BIT_VECTOR when a multi-valued logic
    system is required
  • STD_LOGIC and STD_LOGIC _VECTOR must be used when
    tri-state logic (Z) is required
  • To be able to use this new type, you need to add
    2 lines to your code
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL

21
1164 Types
  • std_logic and std_logic_vector are the industry
    standard logic type for digital design
  • Values for Simulation Synthesis
  • 0 -- Forcing 0
  • 1 -- Forcing 1
  • Z -- High Impedance
  • L -- Weak 0
  • H -- Weak 1
  • - -- Dont care
  • Values for Simulation only (std_ulogic)
  • U -- Uninitialized
  • X -- Forcing Unknown
  • W -- Weak Unknown

22
Entity Declaration Example
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY black_box IS PORT (
  • clk, rst IN std_logic
  • d IN std_logic_vector(7 DOWNTO 0)
  • q OUT std_logic_vector(7 DOWNTO 0)
  • co OUT std_logic)
  • END black_box

23
Exercise 1 The Entity - A Walk through
  • Write an entity declaration for the following
  • Port D is a 12-bit bus, input only
  • Port OE and CLK are each input bits
  • Port AD is a 12-bit, three-state bi-directional
    bus
  • Port A is a 12-bit bus, output only
  • Port INT is a three-state output
  • Port AS is an output also used internally

my_design
ad110
d110
a110
oe
int
clk
as
24
Exercise 1 Solution
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY my_design IS PORT (
  • d IN std_logic_vector(11 DOWNTO 0)
  • oe, clk IN std_logic
  • ad INOUT std_logic_vector(11 DOWNTO 0)
  • a OUT std_logic_vector(11 DOWNTO 0)
  • int OUT std_logic
  • as BUFFER std_logic)
  • END my_design
  • -- In this presentation, VHDL keywords
  • -- are highlighted in bold, CAPITALS
  • -- however, VHDL is not case sensitive
  • -- clock, Clock, CLOCK all refer to the
  • -- same signal, -- means a comment

25
The Architecture
  • Architectures describe what is in the black box
    (i.e., the structure or behavior of entities)
  • Descriptions can be either a combination of
  • Structural descriptions
  • Instantiations (placements of logic-much like in
    a schematic-and their connections) of building
    blocks referred to as components
  • Behavioral/Dataflow descriptions
  • Algorithmic (or high-level) descriptions
  • IF a b THEN state lt state5
  • Boolean equations (also referred to as dataflow)
  • x lt a OR (b AND c)

26
The Architecture Declaration
  • ARCHITECTURE arch_name OF entity_name IS
  • -- optional signal declarations, etc.
  • BEGIN
  • --VHDL statements
  • END arch_name
  • arch_name is an arbitrary name
  • optional signal declarations are used for signals
    local to the architecture body (that is, not the
    entitys I/O).
  • entity_name is the entity name
  • statements describe the function or contents of
    the entity


27
Architecture Body Styles Behavioral
  • ENTITY compare IS PORT (
  • a, b IN std_logic_vector(0 TO 3)
  • equals OUT std_logic)
  • END compare
  • ARCHITECTURE behavior OF compare IS
  • BEGIN
  • comp PROCESS (a,b)
  • BEGIN
  • IF a b THEN
  • equals lt '1'
  • ELSE
  • equals lt '0'
  • END IF
  • END PROCESS comp
  • END behavior

28
Architecture Body Styles Dataflow
  • ENTITY compare IS PORT (
  • a, b IN std_logic_vector(0 TO 3)
  • equals OUT std_logic)
  • END compare
  • ARCHITECTURE dataflow OF compare IS
  • BEGIN
  • equals lt '1' WHEN a b ELSE '0'
  • END dataflow

29
Architecture Body Styles Structural
  • ENTITY compare IS PORT (
  • a, b IN std_logic_vector(0 TO 3)
  • equals OUT std_logic)
  • END compare
  • USE WORK.gatespkg.ALL
  • ARCHITECTURE structure OF compare IS
  • SIGNAL x std_logic_vector (0 to 3)
  • BEGIN
  • u0 xnor2 PORT MAP (a(0),b(0),x(0))
  • u1 xnor2 PORT MAP (a(1),b(1),x(1))
  • u2 xnor2 PORT MAP (a(2),b(2),x(2))
  • u3 xnor2 PORT MAP (a(3),b(3),x(3))
  • u4 and4 PORT MAP (x(0),x(1),x(2),x(3),equals)
  • END structure

30
Mixing Architecture Styles
  • The various styles may be mixed in one
    architecture.

ENTITY logic IS PORT ( a,b,c IN
std_logic f OUT std_logic) END logic USE
WORK.gatespkg.ALL ARCHITECTURE archlogic OF
logic IS SIGNAL d std_logic BEGIN d lt a
AND b g1 nor2 PORT MAP (c, d, f) END
archlogic
g1
Behavioral/Dataflow
Structural
31
Comparing Architecture Styles
  • These examples synthesize to equivalent circuits
  • In more elaborate designs, some descriptions may
    yield more efficient circuits
  • sloppy code inefficient results (see section
    3.3.4)
  • Use styles that make your designs easier to
    describe and maintain
  • Behavioral/Dataflow exploit module generation
    (described later)
  • Structural descriptions may make the design less
    portable (may rely on a library of
    vendor-specific components)

32
Module Generation
  • In Warp release 4.0, a package called std_arith
    can be used to overload the arithmetic (, -,
    etc.) and relational operators (, /, lt, etc.,)
    for std_logic, std_logic_vector and integer types
  • Using this package causes adders, counters,
    comparators, etc., to automatically replace the
    operators in the design. These are optimized for
    the target architecture and synthesis goal
    (area/speed)
  • This is known as module generation

33
Ultragen Synthesis
The VHDL code below describes a comparator
Pre-optimized Circuits
if (a b) then c lt 1 else c lt 0 end if
Warp chooses the best pre-optimized circuit to
meet your design goals
34
A Simple Counter
LIBRARY ieee USE ieee.std_logic_1164.ALL USE
WORK.std_arith.ALL ENTITY count8 IS PORT
( clk IN std_logic count BUFFER
std_logic_vector(7 DOWNTO 0)) END count8
ARCHITECTURE arch_count8 OF count8
IS BEGIN upcount PROCESS (clk) BEGIN IF
clkEVENT and clk1 THEN count lt count
1 END IF END PROCESS upcount END
arch_count8
35
VHDL Statements
  • There are two types of statements, Concurrent
    and Sequential
  • Concurrent Statements (means in parallel)
  • Concurrent statements are executed concurrently
    (at the same time)
  • The order of concurrent statements is not
    important
  • Most of the examples we have seen so far have
    been concurrent statements
  • Boolean Equations
  • WHEN-ELSE
  • WITH-SELECT-WHEN

36
VHDL Statements (cont.)
  • Sequential Statements (means in series)
  • Sometimes we need to model complex functions. In
    that case, we can use an algorithm or model to
    describe the function. This is done with
    Sequential Statements
  • With Sequential statements, the ORDER of the
    statements is important (example later)
  • Therefore, we use a process to mark the beginning
    and end of a block of sequential statements
  • Each completed process is considered to be one
    big concurrent statement (there can be many
    processes inside one architecture)

37
What is a VHDL Process ?
  • Processes are either awake or asleep (active or
    inactive)
  • A process normally has a sensitivity list
  • When a signal in that sensitivity list changes
    value, the process wakes up and all of the
    sequential statements are executed
  • For example, a process with a clock signal in its
    sensitivity list will become active on changes of
    the clock signal
  • At the end of the process, all outputs are
    assigned and the process goes back to sleep until
    the next time a signal changes in the sensitivity
    list

38
The Process (contd.)
  • label PROCESS (sensitivity list)
  • -- variable declarations
  • BEGIN
  • -- sequential statements
  • END PROCESS label
  • The process label and variable declarations are
    optional
  • The process executes when one of the signals in
    the sensitivity list has an event

39
Combinational Logic
  • Can be described with concurrent statements
  • boolean equations
  • when-else
  • with-select-when
  • component instantiatons
  • Can be described with sequential statements
  • if-then-else
  • case-when

40
Combinational Logic w/ Boolean Equations
  • Boolean Equations can be used in both concurrent
    and sequential signal assignment statements.
  • A 4-1 multiplexer is shown below
  • x lt (a AND NOT(s(1)) AND NOT(s(0))) OR
  • (b AND NOT(s(1)) AND s(0)) OR
  • (c AND s(1) AND NOT(s(0))) OR
  • (d AND s(1) AND s(0))

s
2
a
x
b
mux
c
d
41
Selective Signal Assignmentwith-select-when
  • Assignment based on a selection signal
  • WHEN clauses must be mutually exclusive
  • Use a WHEN OTHERS when all conditions are not
    specified
  • Only one reference to the signal, only one
    assignment operator (lt)
  • WITH selection_signal SELECT
  • signal_name lt value_1 WHEN value_1 of
    selection_signal,
  • value_2 WHEN value_2 of selection_signal,
  • ...
  • value_n WHEN value_n of selection_signal,
  • value_x WHEN OTHERS

42
Combinational Logic w/ Selective Signal
Assignment
  • The same 4-1 multiplexer is shown below
  • with s select
  • x lt a when 00 ,
  • b when 01 ,
  • c when 10 ,
  • d when others

s
2
a
x
b
mux
c
d
43
More on with-select-when
  • You can use a range of values
  • with int_value select
  • x lt a when 0 to 3,
  • b when 4 6 8 ,
  • c when 10 ,
  • d when others

44
Conditional Signal Assignmentwhen-else
  • Signal is assigned a value based on conditions
  • Any simple expression can be a condition
  • Priority goes in order of appearance
  • Only one reference to the signal, only one
    assignment operator (lt)
  • Use a final ELSE to avoid latches

signal_name lt value_1 WHEN condition1
ELSE value_2 WHEN condition2
ELSE ... value_n WHEN condition N
ELSE value_x
45
Combinational Logic w/ Conditional Signal
Assignment
  • The same 4-1 multiplexer is shown below
  • x lt a when (s 00) else
  • b when (s 01) else
  • c when (s 10) else
  • d

s
2
a
x
b
mux
c
d
46
Combinational Logic w/ Conditional Signal
Assignment
  • The when conditions do not have to be mutually
    exclusive (as in with-select-when)
  • A priority encoder is shown below
  • j lt w when (a 1) else
  • x when (b 1) else
  • y when (c 1) else
  • z when (d 1) else
  • 000

47
Combinatorial Logic w/ Sequential Statements
  • Grouped together with Processes
  • Processes are concurrent with one another and
    with concurrent statements
  • Order of sequential statements does make a
    difference in synthesis

48
Sequential Statements if-then-else
  • Used to select a set of statements to be executed
  • Selection based on a boolean evaluation of a
    condition or set of conditions
  • Absence of ELSE results in implicit memory
  • IF condition(s) THEN
  • do something
  • ELSIF condition_2 THEN -- optional
  • do something different
  • ELSE -- optional
  • do something completely different
  • END IF

49
if-then-else
  • 4-1 mux shown below
  • mux4_1 process (a, b, c, d, s)
  • begin
  • if s 00 then x lt a
  • elsif s 01 then x lt b
  • elsif s 10 then x lt c
  • else x lt d
  • end if
  • end process mux4_1

s
2
a
x
b
mux
c
d
50
Sequential Statements Case-When
  • CASE selection_signal IS
  • WHEN value_1_of_selection_signal gt
  • (do something) -- set of statements 1
  • WHEN value_2_of_selection_signal gt
  • (do something) -- set of statements 2
  • ...
  • WHEN value_N_of_selection_signal gt
  • (do something) -- set of statements N
  • WHEN OTHERS gt
  • (do something) -- default action
  • END CASE

51
The CASE Statement 4-1 Mux
  • ARCHITECTURE archdesign OF design IS
  • SIGNAL s std_logic_vector(0 TO 1)
  • BEGIN
  • mux4_1 PROCESS (a,b,c,d,s)
  • BEGIN
  • CASE s IS
  • WHEN "00" gt x lt a
  • WHEN "01" gt x lt b
  • WHEN "10 gt x lt c
  • WHEN OTHERS gt x lt d
  • END CASE
  • END PROCESS mux4_1
  • END archdesign

s
2
a
x
b
mux
c
d
52
Signal Assignment in ProcessesWhich Circuit is
Correct?
  • ARCHITECTURE arch_reg OF reg IS
  • SIGNAL b std_logic
  • reg2 PROCESS
  • BEGIN
  • WAIT UNTIL clock '1' -- implied
    sensitivity list
  • b lt a -- after the rising clock edge, a goes
    to b c lt b -- after the rising clock edge, b
    goes to c
  • END PROCESS reg2
  • END arch_reg

c
b
a
clock
53
Signal Assignment in Processes
  • Inside processes, signals are not updated
    immediately. Instead, they are scheduled to be
    updated
  • The signals are not actually updated until the
    END PROCESS statement is reached
  • Therefore, on the previous slide, two registers
    will be synthesized (c lt b will be the old b)
  • In some cases, the use of a concurrent statement
    outside the process will fix the problem, but
    this is not always possible
  • So how else can we fix this problem ?

54
Variables
  • When a concurrent signal assignment outside the
    process cannot be used, the previous problem can
    be avoided using a variable
  • Variables are like signals, BUT they can only be
    used inside a PROCESS. They cannot be used to
    communicate information between processes
  • Variables can be of any valid VHDL data type
  • The value assigned to a variable is available
    immediately
  • Assignment of variables is done using a colon
    (), like this
  • c a AND b

55
Using Variables vs. Signals
  • Solution using a variable within a process

-- assume a and c are signals defined
elsewhere ARCHITECTURE arch_reg OF reg
IS PROCESS VARIABLE b std_logic BEGIN WAIT
UNTIL clock '1' b a -- this is
immediate c lt b -- this is scheduled END
PROCESS END arch_reg
56
Native Operators
  • Logical - defined for type bit, bit_vector,
    boolean
  • AND, NAND
  • OR, NOR
  • XOR, XNOR
  • NOT
  • Relational - defined for types bit, bit_vector,
    integer
  • (equal to)
  • / (not equal to)
  • lt (less than)
  • lt (less than or equal to)
  • gt (greater than)
  • gt (greater than or equal to)
  • overloaded for std_logic, std_logic_vector

57
Native Operators (contd.)
  • Unary Arithmetic - defined for type integer
  • - (arithmetic negate)
  • Arithmetic - defined for type integer
  • (addition), (multiplication)
  • - (subtraction)
  • Concatenation - defined for strings
  • Note, a STRING is any sequence of characters,
    therefore a std_logic_vector is an example of a
    STRING
  • overloaded for std_logic, std_logic_vector

58
Overloaded Operators
  • In VHDL, the scope of all of the previous
    operators can be extended (or overloaded) to
    accept any type supported by the language, e.g.,
  • -- assume a declaration of a 16-bit vector as
  • SIGNAL pc IS std_logic_vector(15 DOWNTO 0)
  • -- then a valid signal assignment is
  • pc lt pc 3
  • -- assuming the '' operator has been overloaded
    to --- accept std_logic_vector and integer
    operands
  • The std_logic_1164 package defines overloaded
    logical operators (AND, OR, NOT, etc.,) for the
    std_logic and std_logic_vector types
  • In this training, you will learn to use
    overloaded operators, but not to define them

59
Legal VHDL Identifiers
  • Letters, digits, and underscores only (first
    character must be a letter)
  • The last character cannot be an underscore
  • Two underscores in succession are not allowed
  • Using reserved words is not allowed (the VHDL
    editor will highlight reserved words for this
    reason)
  • Examples
  • Legal
  • tx_clk, Three_State_Enable, sel7D, HIT_1124
  • Not Legal
  • _tx_clk, 8B10B, largenum, case, clk_

60
The Warp Design Environment
  • Using the Project Wizard
  • Entering Project Name / Path
  • Adding Files to the Project
  • Selecting a Device
  • Opening up a File for Editing
  • Additional Tools Review
  • Describing the left hand files pane
  • Overview of Pull down menus
  • Reviewing On-line Help

61
Using the Project Wizard
  • Open Galaxy
  • Using the ltfilegt pull down menu, select ltnewgt
  • Select Project - Target Device, then ltokgt

62
Entering Project Name / Path
  • In the Project Name dialog box, enter
    exercise2, then ltokgt
  • In the Project Path dialog box, browse to
    C\warp\class, then select ltnextgt

63
Adding Files to the Project
  • Highlight ex2.vhd, select ltaddgt then ltokgt

64
Selecting a Device
  • Double click on Small PLDs
  • Select 22V10 on the left and PALCE22V10-5JC
    on the right, then hit ltfinishgt, then ltokgt

65
Opening up a File for Editing
  • In the left hand pane, double click on ex2.vhd.
    This will open the file up in the editor on the
    right

66
Exercise 2 Architecture Declaration of a
Comparator
  • The entity declaration is as follows

LIBRARY ieee USE ieee.std_logic_1164.ALL ENTI
TY compare IS PORT ( a, b IN
std_logic_vector(3 DOWNTO 0) aeqb OUT
std_logic) END compare
a(30)
aeqb
b(30)
  • Write an architecture that causes aeqb to be
    asserted when a is equal to b
  • Multiple solutions exist

67
Three possible solutions
  • Concurrent statement solution using a conditional
    assignment

ARCHITECTURE arch_compare OF compare
IS BEGIN aeqb lt '1' WHEN a b ELSE '0' END
arch_compare
  • Concurrent statement solution using boolean
    equations

ARCHITECTURE arch_compare OF compare
IS BEGIN aeqb lt NOT( (a(0) XOR b(0))
OR (a(1) XOR b(1)) OR (a(2) XOR b(2))
OR (a(3) XOR b(3))) END arch_compare
68
Three possible solutions (contd.)
  • Solution using a process with sequential
    statements

ARCHITECTURE arch_compare OF compare
IS BEGIN comp PROCESS (a, b) BEGIN IF a
b THEN aeqb lt '1' ELSE aeqb lt
'0' END IF END PROCESS comp END
arch_compare
69
Using Tri-State Logic
  • ENTITY test_three IS
  • PORT( oe IN std_logic
  • data OUT std_logic_vector(0 to 7))
  • END test_three
  • ARCHITECTURE archtest_three OF test_three IS
  • BEGIN
  • PROCESS (oe)
  • BEGIN
  • IF (oe '1')
  • THEN data lt "01100100"
  • ELSE data lt "ZZZZZZZZ"
  • END IF
  • END PROCESS
  • END archtest_three

70
Behavioral Dont Cares
  • Warp uses explicit "dont care" conditions to
    produce optimal logic equations
  • IF (a '1') AND (b '1') THEN
  • x lt c
  • ELSE
  • x lt '-'
  • END IF
  • Produces the equation x c
  • To assign dont cares in VHDL mysig lt '-'
  • 'X' means "unknown" and is not useful for
    synthesis

71
Comparing Vectors to Strings-more on don't cares-
  • Comparing "1101" to "11-1" will return FALSE
  • Use std_match(a,"string")
  • Must include std_arith package
  • Example
  • ...
  • signal a std_logic_vector (1 to 4)
  • ...
  • IF std_match(a,"10-1") THEN
  • x lt '1'
  • END IF

72
Additional Tools Review
  • Describing the left hand files pane
  • Source File Listing
  • Design Hierarchy
  • Output File Listing
  • Pull down menus
  • File, Edit, View, Format, Project, Compile,
    Templates, Bookmarks, Tools, Window, Help
  • On-line Help

73
Source File Listing
  • Click on the leftmost tab on the bottom of the
    left hand pane
  • All source files for the current project will be
    displayed
  • Double click on any file to open it up in the
    editor window on the right

74
Hierarchy Listing
  • Click on the centermost tab on the bottom of the
    left hand pane
  • The project hierarchy will be displayed

75
Output File Listing
  • Click on the rightmost tab on the bottom of the
    left hand pane
  • All output files for the current project will be
    displayed
  • Double click on any file to open it up in the
    editor window on the right
  • By selecting a sub-heading within a file, the
    editor will go to that section

76
Lower Status Windows
  • The lower window pane of Galaxy displays the
    following
  • Compiler - A line by line account of the entire
    compilation process. If an error is shown, you
    can jump into the proper file and line by double
    clicking on the error.
  • Errors Warnings - This tab only shows errors
    warnings
  • Search in files - Shows all occurrences generated
    by search in files button

77
Pull-down Menus
  • Files Menu - Allows the opening or closing of
    files and projects, printing, and recalling of
    prior files and projects

78
Pull-down Menus
  • Edit Menu - Typical Cut, Copy and Paste commands
    as well as Find, Replace and Search all files.
    Additionally, the editor and project user
    preferences dialog box can be selected.

79
Output File Listing
  • The Preferences screen allows the user to select
    editor options such as autosave, font size, tab
    spacing and highlighting. Additionally, project
    settings can be set up as well

80
Pull-down Menus
  • View Menu - Allows the user to select several
    viewing options such as viewing pane options and
    toolbars
  • Format Menu - Allows block comment / un-comment
    as well as the setting of tabs

81
Pull-down Menus
  • Project Menu - Used to add and remove files from
    a project and perform library management.
    Additionally the user can select/change device
    types, set compiler options, set a project as the
    top level in a hierarchy as well as back annotate
    pins and nodes to a control file.

82
Compiler Options
  • The Compiler options screen allows the user to
    choose generic attributes for his file such as
    area/speed and optimization effort, I/O voltage,
    slew rate and bus hold. Additionally technology
    mapping attributes can be set. Finally, the
    timing model output and test bench output formats
    can be selected.

83
Pull-down Menus
  • Compile Menu - Allows the user to compile the
    selected file or the entire project.
  • Templates Menu - The user can browse through VHDL
    constructs or place LPM modules within his VHDL
    code.
  • Bookmarks Menu - Allows the user to add and
    recall bookmarks within his files.
  • Tools Menu - Launches the Jam Composer, Aldec
    Simulator and Aldec FSM Editor

84
Pull-down Menus
  • Window Menu - Allows positioning of files within
    the edit window as well as swapping between
    tabbed windows.
  • Help Menu - Access to on-line help and device
    selector guide.

85
Exercise 3The Schematic
86
Exercise 3
  • Use Warp to compile the VHDL design description
    of the truth table below
  • Write the Architecture for the given Entity
    (next)
  • Save design in file named ex3.vhd

87
Exercise 3The Entity Declaration
  • the entity declaration is as follows

LIBRARY ieee USE ieee.std_logic_1164.ALL ENTI
TY ex3 IS PORT ( addr IN
std_logic_vector(1 DOWNTO 0) nvalid IN
std_logic en BUFFER std_logic_vector(0
TO 3) dir OUT std_logic ) END
ex3
88
Exercise 3 Instructions
  • Create a new project using the Project Wizard
  • Choose ltfilegt, ltnewgt, ltProject - Target Devicegt
  • Name your project exercise3, click ltNextgt
  • Select the file ex3.vhd and ltAddgt it to the
    project
  • To choose a device In the left hand window,
    double click on the SPLD folder, then single
    click on the 22V10 folder. In the right hand
    window, select a PALCE22V10-5PC. Note that the
    details of the device are outlined below. Click
    ltFinishgt
  • Double click on the ex3.vhd folder in the left
    hand window to open the file up into the editor
    window on the right.

89
Exercise 3 Instructions (contd.)
  • To designate that ex3.vhd is the top level
    design, either choose ltProjectgt ltSet Topgt or hit
    the shortcut button.
  • Output an 1164/VHDL timing file by selecting
    ltProjectgt ltCompiler Optionsgt. In the Simulation
    Timing Model box, select 1164/VHDL
  • Modify the code in the editor window on the right
    to perform the function shown in the prior truth
    table.
  • To compile your design, either choose ltCompilegt
    ltSelectedgt or hit the shortcut button.
  • If an error appear in the lower window, double
    click on it to highlight the location of the
    error in the editor.
  • Re-compile until all errors are gone

90
Exercise 3 Instructions (contd.)
  • Simulate the design using the Aldec simulator
  • Select ltToolsgt ltActive-HDL Simgt
  • Select ltFilegt ltOpen VHDLgt and select
    c\warp\class\vhd\ex3.vhd
  • Select ltFilegt ltOpen Waveformgt and select
    c\warp\class\wave_ex3.awf
  • Assure the Time To Run is 200ns
  • Run the simulator ltF5gt or
  • Review against output on the following page
  • Reference the application note handout for
    additional details

91
Exercise 3 Aldec Simulator Waveform
92
Exercise 3 The Solution
  • The architecture is as follows

ARCHITECTURE archex3 OF ex3 IS BEGIN en(0) lt
'0' WHEN (addr "00" AND nvalid '0') ELSE
'1' en(1) lt (NOT addr(1)) AND addr(0) AND (NOT
nvalid) en(2) lt '0' WHEN (addr "10" AND
nvalid '0') ELSE '1' en(3) lt addr(1) AND
addr(0) AND (NOT nvalid) dir lt '0' WHEN (addr
"00" AND nvalid '0') OR (addr "10" AND
nvalid '0') ELSE '1' END archex3
93
Aggregates and Subscripts
  • An aggregate assignment concatenates signals
    together
  • Good for creating a bus from several inputs
  • The concatenation operator can be used as well
  • tmp lt (a,b,c,d)
  • tmp lt a b c d
  • Signals can be pulled from larger vectors
  • Good for grouping outputs as an alias
  • Sizes on both sides of assignment must match
  • rw lt ctrl(0) ce lt ctrl(1) oe lt ctrl(2)
  • highcount lt count(7 DOWNTO 4)

94
Exercise 3 Alternate Solution
  • Using With/Select and aggregates

ARCHITECTURE archex3 OF ex3 IS SIGNAL control
std_logic_vector(2 DOWNTO 0) SIGNAL
outputs std_logic_vector(0 TO 4) BEGIN
control lt addr nvalid WITH control
SELECT outputs lt "00100" WHEN "000",
"10101" WHEN "001",
"11101" WHEN "010",
"10101" WHEN "011", "10000"
WHEN "100", "10101" WHEN
"101", "10111" WHEN "110",
"10101" WHEN "111",
"-----" WHEN OTHERS en lt outputs(0 TO
3) dir lt outputs(4) END archex3
95
Synchronous Logic
  • PLDs work well in synchronous applications
  • Two methods of creating synchronous logic
  • Structurally
  • instantiating components with registers
  • Behaviorally
  • Using a processes with a clock signal in the
    sensitivity list

96
Registers in Behavioral VHDL
  • Example a D-type flip-flop
  • ENTITY registered IS PORT (
  • d, clk IN std_logic
  • q OUT std_logic)
  • END registered
  • ARCHITECTURE archregistered OF registered IS
  • BEGIN
  • flipflop PROCESS (clk)
  • BEGIN
  • IF rising_edge(clk)
  • THEN q lt d
  • END IF
  • END PROCESS flipflop
  • END archregistered

97
Registers in Behavioral VHDL
  • The synthesis compiler infers that a register is
    to be created for which signal q is the output
    because
  • The clock (clk) is in the sensitivity list
  • The construct, rising_edge(clk),
    falling_edge(clk) or clkevent AND clock1
    appears in the process
  • The rising_edge(clk) or falling_edge(clk)
    statement implies that subsequent signal
    assignments occur on the rising/falling edge of
    the clock
  • The absence of an else clause in the if-then
    statement implies that if the clkevent and clk
    1 condition is not fulfilled (i.e. not a
    rising-edge), q will retain its value until the
    next assignment occurs (this is referred to as
    implied memory)

98
Rising/Falling Edge Functions
  • The 1164 package defines 2 functions for edge
    detection
  • rising_edge (signal)
  • similar to (signalevent and signal 1)
  • falling_edge (signal)
  • similar to (signalevent and signal 0)
  • if rising_edge(clk) then
  • q lt d
  • end if

99
A Registered Process (1)
  • A 4-bit counter with synchronous reset

USE WORK.std_arith.ALL ... upcount PROCESS
(clk) BEGIN IF rising_edge(clk) THEN IF
reset '1' THEN count lt "0000" -- or
x"0" instead ELSE count lt count 1 END
IF END IF END PROCESS upcount
  • This process is only sensitive to changes in
    clk, i.e., it will become active only when the
    clock transitions

100
A Registered Process (2)
  • A 4-bit counter with asynchronous reset

USE WORK.std_arith.ALL ... upcount PROCESS
(clk, reset) BEGIN IF reset '1' THEN
count lt x"0" ELSIF rising_edge(clk)
THEN count lt count 1 END IF END PROCESS
upcount
  • This process is sensitive to changes in both clk
    and rst, i.e., it will become active during
    clock or reset transitions.

101
A Registered Process (3)
  • A 4-bit loadable counter with asynchronous reset

USE WORK.std_arith.ALL ... upcount PROCESS
(clk, reset) BEGIN IF reset '1 THEN
count lt x"0" ELSIF rising_edge(clk)
THEN IF load '1' THEN count lt
data ELSE count lt count 1 END
IF END IF END PROCESS upcount
data
count
load
clk
rst
102
Creating a level-sensitive latch
  • Instead of using the rising_edge or falling_edge
    function, replace it with clk1 or clk0 and
    put d in the sensitivity list
  • latch PROCESS (clk, d)
  • BEGIN
  • IF clk '1'
  • THEN q lt d
  • END IF
  • END PROCESS latch

103
Instantiating a registered component
  • Example Using LPM library
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • USE WORK.lpmpkg.all
  • ENTITY registered IS PORT (
  • d IN std_logic
  • clk IN std_logic_vector(3 DOWNTO 0)
  • q OUT std_logic _vector(3 DOWNTO 0))
  • END registered
  • ARCHITECTURE archregistered OF registered IS
  • BEGIN
  • flipflop Mff generic map (lpm_widthgt4,lpm_fft
    ypegtlpm_dff)
  • PORT MAP (datagtd,clockgtclk,enablegtone,qgtq)
  • END archregistered

104
The WAIT statement
  • This is another method to activate a process
  • The WAIT statement is a sequential statement
    which suspends the execution of a process until
    the condition specified becomes valid (true)
    i.e., an implied sensitivity list, e.g.,

sync PROCESS BEGIN WAIT UNTIL
clock'1' IF enable'1' THEN q_out lt
d_in ELSE q_out lt '0' END IF END
PROCESS sync
105
Implicit memory
  • Signals in VHDL have a current value and may be
    scheduled for a future value
  • If the future value of a signal cannot be
    determined, a latch will be synthesized to
    preserve its current value
  • Advantages
  • Simplifies the creation of memory in logic design
  • Disadvantages
  • Can generate unwanted latches, e.g., when all of
    the options in a conditional sequential statement
    are not specified

106
Implicit memoryExample of incomplete
specification
ARCHITECTURE archincomplete OF incomplete IS
BEGIN im_mem PROCESS (a,b) BEGIN IF a
'1' THEN c lt b END IF END PROCESS
im_mem END archincomplete
  • Note the incomplete specification of the
    IF...THEN... statement causes a latch to be
    synthesized to store the previous state of c

107
Implicit memory Example of complete specification
ARCHITECTURE archcomplete OF complete IS
BEGIN no_mem PROCESS (a, b) BEGIN IF a
'1' THEN c lt b ELSE c lt
'0' END IF END PROCESS no_mem END
archcomplete
  • The conditional statement is fully specified, and
    this causes the process to synthesize to a single
    gate

108
The rules to avoid implicit memory
  • To avoid the generation of unexpected latches
  • always terminate an IF...THEN... statement with
    an ELSE clause
  • cover all alternatives in a CASE statement
  • define every alternative individually, or
  • terminate the CASE statement with a WHEN
    OTHERS... clause, e.g.,
  • CASE coin_inserted IS
  • WHEN quarter gt totallttotal25
  • WHEN dime gt totallttotal10
  • WHEN nickel gt totallttotal5
  • WHEN OTHERS gt totallttotal
  • errorlt1
  • END CASE

109
Exercise 4
  • Making use of the previous examples, write an
    entity/architecture pair for the following design

ENC
COUNTER
DATA
DIN
4
COUNT
LD
LD
Q
4
ENC
COMPARATOR
CLOCK
P
RST
RESET (sync)
PQ
Q
REGISTER
DIN
Q
4
ENR
ENR
110
Exercise 4 Instructions
  • Create a new project using the Project Wizard
  • Choose ltfilegt, ltnewgt, ltProject - Target Devicegt
  • Name your project exercise4, click ltNextgt
  • Select the file ex4.vhd and ltAddgt it to the
    project
  • The target device is 32 Macrocell 8.5 ns CPLD in
    a 44 pin TQFP package. Choose CY7C371I-143AC
  • Modify the code in the editor window on the right
    to perform the function shown in the prior
    diagram.
  • Hints
  • Use 2 processes and a concurrent statement
  • Use the register, counter, and comparator shown
    previously
  • Incorporate count enable logic in count process

111
Exercise 4 Instructions (contd.)
  • To simulate your design with the Aldec Simulator,
    open the VHDL file C\warp\class\vhd\ex4.vhd and
    then select ltSimulationgt ltInitialize Simulationgt
  • Add all of the signals by selecting ltWaveformgt
    ltAdd Signalsgt (or using the shortcut ).
    When the window opens, double click on each
    signal in the right hand box until all signals
    are added.
  • Enter the stimulus found on the following page,
    reference the applications note handed out in
    class for additional details

112
Exercise 4 Instructions (contd.)
  • Add the following stimulus
  • reset lt formula 1 0, 0 20 ns, 1 300 ns
  • clock lt clock of 100 MHz
  • enr lt formula 0 0, 1 70 ns, 0 80 ns
  • ld lt formula 0 0, 1 120 ns, 0 130 ns
  • data lt 0000 0, 1100 50 ns, 163 100 ns, 160
    150 ns
  • enc lt formula 0 0, 1 160 ns
  • After completing your design, back annotate the
    pin numbers by choosing ltProjectgt ltAnnotategt and
    then ltOKgt. To view the back annotated pins,
    select ltViewgt ltControl Filegt from the pull down
    menus

113
Exercise 4 Additional Help
  • To get help on the format for adding stimulators
    (or any other topic), open up the stimulator
    dialog box and click on the question mark in the
    upper right corner ( ) then in the Enter
    Formula box.

114
Exercise 4 Aldec Simulator Waveform
115
Exercise 4 Solution
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY ex4 IS PORT (
  • clock, reset, enc, enr, ld IN std_logic
  • data IN std_logic_vector (3 DOWNTO
    0)
  • count BUFFER std_logic_vector(3
    DOWNTO 0))
  • END ex4
  • USE WORK.std_arith.ALL -- for counter and
    Ultragen
  • ARCHITECTURE archex4 OF ex4 IS
  • SIGNAL comp std_logic
  • SIGNAL regout std_logic_vector (3 DOWNTO 0)
  • BEGIN
  • reg PROCESS (clock)
  • BEGIN
  • IF RISING_EDGE(clock)
  • THEN
  • IF enr '1' THEN
  • regout lt data
  • END IF

116
Exercise 4 Solution (contd.)
  • cntr PROCESS (clock)
  • BEGIN
  • IF RISING_EDGE(clock) THEN
  • IF reset '1'
  • THEN count lt "0000"
  • ELSIF ld '1'
  • THEN count lt data
  • ELSIF enc '1' AND comp '0'
  • THEN count lt count 1
  • END IF
  • END IF
  • END PROCESS cntr
  • comp lt '1' WHEN regout count ELSE '0'
  • END archex4

117
Exercise 4 Control File
  • Ex4.ctl
  • Attribute PIN_NUMBERS of count(1) is "37"
  • Attribute PIN_NUMBERS of count(2) is "30"
  • Attribute PIN_NUMBERS of data(2) is "29"
  • Attribute PIN_NUMBERS of data(1) is "27"
  • Attribute PIN_NUMBERS of data(0) is "26"
  • Attribute PIN_NUMBERS of count(3) is "25"
  • Attribute PIN_NUMBERS of count(0) is "18"
  • Attribute PIN_NUMBERS of data(3) is "15"
  • Attribute PIN_NUMBERS of ld is "14"
  • Attribute PIN_NUMBERS of enc is "13"
  • Attribute PIN_NUMBERS of reset is "12"
  • Attribute PIN_NUMBERS of clock is "7"
  • Attribute PIN_NUMBERS of enr is "4"

118
State machines
  • Moore Machines
  • A finite state machine in which the outputs
    change due to a change of state
  • Mealy Machines
  • A finite state machine in which the outputs can
    change asynchronously i.e., an input can cause an
    output to change immediately

119
Moore machines
  • Outputs may change only with a change of state
  • Multiple implementations include
  • Arbitrary state assignment
  • outputs must be decoded from the state bits
  • combinatorial decode
  • registered decode
  • Specific state assignment
  • outputs may be encoded within the state bits
  • one-hot encoding

120
Example A Traffic Light Controller
  • Lets take a look at an example state machine and
    see how to describe it using the 3 types of
    implementations

TIMER3
TIMER2
RESET (asynchronous)
TIMER1
TIMER2
RED
GREEN
YELLOW
TIMER1
TIMER3
121
Moore state machine implementations (1)
  • Outputs decoded from state bits COMBINATORIALLY
  • combinatorial output logic is in series with
    state registers
  • outputs are a function of the present state only
  • time from clock to output (tco) is long

Present State
Next State Logic
Next State
Outputs
State Registers
Inputs
Tco tpd
122
Example The Entity Declaration
  • The entity declaration remains exactly the same
    for each implementation.
  • For example
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY state_machine IS PORT (
  • clock, reset IN std_logic
  • timer1, timer2, timer3 IN std_logic
  • r, y, g OUT std_logic)
  • END state_machine

123
Example Solution 1
  • Combinatorial outputs decoded from the state
    registers

ARCHITECTURE arch_1 OF state_machine IS TYPE
traffic_states IS (red, yellow, green) --
enumerated type SIGNAL sm traffic_states BEG
IN fsm PROCESS (clock, reset) -- the process
describes the BEGIN --
state machine only IF reset '1' THEN
sm lt red ELSIF rising_edge(clock)
THEN CASE sm IS WHEN red gt IF
timer11 THEN sm lt green
ELSE sm lt red END IF
WHEN green gt IF timer21' THEN sm
lt yellow ELSE sm lt green
END IF
124
Example Solution 1 (contd.)
  • WHEN yellow gt IF timer31
  • THEN sm lt red
  • ELSE sm lt yellow
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • -- the outputs are decoded from the state
    machine
  • -- registers using combinatorial logic
  • r lt '1' WHEN (sm red) ELSE '0'
  • g lt '1' WHEN (sm green) ELSE '0'
  • y lt '1' WHEN (sm yellow) ELSE '0'
  • END arch_1

125
Moore state machine implementations (2)
  • Outputs decoded from state bits using REGISTERS
  • registered output logic is in parallel with state
    registers
  • outputs are a function of the previous state and
    the inputs
  • tco is shorter, but you need more registers

Present State
State Registers
Next State Logic
Inputs
Outputs
Output Logic
126
Example Solution 2
  • Registered outputs decoded from the state
    registers

ARCHITECTURE arch_2 OF state_machine IS TYPE
traffic_states IS (red, yellow, green) SIGNAL
sm traffic_states BEGIN fsm PROCESS
(clock, reset) -- the process describes
the BEGIN -- state machine
AND the outputs IF reset '1' THEN sm
lt red rlt1 glt0 ylt0
ELSIF rising_edge(clock) THEN CASE sm IS
WHEN red gt IF timer11 THEN sm
lt green
rlt0 glt1 y0 ELSE sm lt
red rlt1
glt0 y0 END IF
127
Example Solution 2 (contd.)
  • WHEN green gt IF timer21'
  • THEN sm lt yellow
  • rlt0 glt0 ylt1
  • ELSE sm lt green
  • rlt0 glt1 ylt0
  • END IF
  • WHEN yellow gt IF timer31'
  • THEN sm lt red
  • rlt1 glt0 ylt0
  • ELSE sm lt yellow
  • rlt0 glt0 ylt1
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF

128
Moore State Machine Implementations (3)
  • We encoded the outputs within the state registers

Red
Green
Yellow
State Encoding
State
1
0
0
100
S0
0
1
0
010
S1
0
0
1
001
S2
Note Both bits of the state encoding are used as
outputs
Outputs
Logic
Inputs
129
Example Solution 3
  • Outputs encoded inside the state registers

ARCHITECTURE arch_3 OF state_machine IS SIGNAL
sm std_logic_vector(2 DOWNTO 0)
CONSTANT red std_logic_vector(2 DOWNTO 0)
100" CONSTANT green
std_logic_vector(2 DOWNTO 0) "010"
CONSTANT yellow std_logic_vector(2 DOWNTO 0)
"001" BEGIN fsm PROCESS (clock, reset)
-- the process describes the BEGIN
-- state machine only IF reset '1'
THEN sm lt red ELSIF
rising_edge(clock) THEN CASE sm IS
WHEN red gt IF timer11 THEN sm lt
green ELSE sm lt red END
IF
130
Example Solution 3 (contd.)
  • WHEN green gt IF timer21'
  • THEN sm lt yellow
  • ELSE sm lt green
  • END IF
  • WHEN yellow gt IF timer31
  • THEN sm lt red
  • ELSE sm lt yellow
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • r lt sm(2) -- the outputs are just taken from
  • g lt sm(1) -- the state machine registers
  • y lt sm(0) -- (no decode logic required)

131
State Machines One-hot Encoding
  • One state per flip-flop
  • in FPGA-type architectures
  • reduces the next state logic
  • requires fewer levels of logic cells
  • enables high-speed state machines (gt 100MHz)
  • in CPLDs
  • reduces the number of product terms
  • can eliminate expander product terms (i.e.
    reduce delays, and increase operating speed)
  • but, uses more macrocells

132
Example One-hot-one Solution
  • Combinatorial outputs decoded from the state
    registers

ARCHITECTURE arch_1 OF state_machine IS TYPE
traffic_states IS (red, yellow, green) --
enumerated type SIGNAL sm traffic_states ATT
RIBUTE state_encoding OF traffic_states TYPE IS
one_hot_one BEGIN fsm PROCESS (clock,
reset) -- the process describes the BEGIN
-- state machine only IF reset
'1' THEN sm lt red ELSIF
rising_edge(clock) THEN CASE sm IS
WHEN red gt IF timer11 THEN sm
lt green ELSE sm lt red END
IF WHEN green gt IF timer21'
THEN sm lt yellow ELSE sm
lt green END IF
133
Example One-hot-one Solution (contd.)
  • WHEN yellow gt IF timer31'
  • THEN sm lt red
  • ELSE sm lt yellow
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • -- the outputs are decoded from the state
    machine
  • -
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