Computer Org - Chapter 5

1
Chapter 5a Single-Cycle CPU DataPath
2
Building A CPU

• Weve built a small ALU
• Add, Subtract, SLT, And, Or
• Could figure out Multiply and Divide...

• What about the rest
• How do we deal with memory and registers?
• What about control operations (branches)?
• How do we interpret instructions?

• The whole thing...
• A CPUs datapath deals with moving data around
• A CPUs control manages the data

5.1
3
Datapath Overview
ALU Computes on R-type 2 registers
I-type Register and data
Current Instruction PC
Instructions R-type 3 registers I-type 2
registers, Data
Memory Address from ALU Data to/from regs
Data to write intodest. register from ALU or
Memory
5.1
4
Instruction Datapath

• Instructions will be held in the instruction
  memory
• The instruction to fetch is at the location
  specified by the PC
• Instr. MPC

4

• After we fetch one instruction, the PC must be
  incremented to the next instruction
• All instructions are 4 bytes
• PC PC 4

Note Regular instruction width (32 for MIPS)
makes this easy
5.2
5
R-type Instruction Datapath
Read reg. num A
Read reg num A
Read reg data A
Read reg num B
Zero
Result
Write reg num
Read reg data B
ALU
Write reg data

• R-type Instructions have three registers
• Two read (Rs, Rt) to provide data to the ALU
• One write (Rd) to receive data from the ALU

• Well need to specify the operation to the ALU
  (later...)
• We might be interested if the result of the ALU
  is zero (later...)

5.2
6
Memory Operations
Read address
Read data
Write address
Write data

• Memory operations first need to compute the
  effective address
• LW t1, 450(s3) E.A. 450 s3
• Add together one register and 16 bits of
  immediate data
• Immediate data needs to be converted from 16-bit
  to 32-bit
• Memory then performs load or store using
  destination register

5.2
7
Branches

• Branches conditionally change the next
  instruction
• BEQ 2, 1, 42
• The offset is specified as the number of words to
  be added to the next instruction (PC4)

Instruction
To controllogic

• Take offset, multiply by 4
• Shift left two

• Add this to PC4 (from PC logic)

offset

• Control logic has to decide if the branch is
  taken
• Uses zero output of ALU

5.2
8
Integrating the R-types and Memory
MemoryDatapath

• R-types and Load/Stores are similar in many
  respects
• Differences
• 2nd ALU source R-types use register, I-types use
  Immediate
• Write Data R-types use ALU result, I-types use
  memory
• Mux the conflicting datapaths together
• Punt on the control logic for now

5.3
9
Adding the instruction memory
Simply add the instruction memoryand PC to the
beginning of the datapath.
Separate Instruction and Data memories are needed
in order to allowthe entire datapath to complete
its job in a single clock cycle.
5.3
10
Adding the Branch Datapath
Now we have the datapath for R-type, I-type, and
branch instructions.
On to the control logic!
5.3
11
When does everything happen?
0
4
Result
1
clk
Add
Result
Sh.Left2
Add
Single-Cycle Design
Read reg. num A
Read reg num A
Read address
Read reg data A
Data Memory
Read reg num B
Read address
PC
Zero
Read data
1
Registers
Instruction 31-0
Write address
Result
Write reg num
InstructionMemory
0
0
Read reg data B
Write data
Write reg data
1
clk
clk
16
32
signextend
Combinational LogicJust does it! Outputs are
always just a function of its inputs (with some
delay)
Registers Written at the end of the clock
cycle. (Rising edge triggered).
5.3