Bring up VxWorks on MIPS Core

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Bring up VxWorks on MIPS Core

• Rockins Chen

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Self-intro
???/Rockins Chen SOHO Line/Network
Dept./TP-LINK ybc2084_at_gmail.com http//rockins.inf
o
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Why VxWorks?

• Pro
• Simplicity
• High quality code
• Document everything

• Con
• Proprietary
• Less existed packages
• Inactive community

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Actually
Code merge
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Basic OS Service of VxWorks

• Multi-Tasking
• Preemptive priority scheduling
• Task control
• Shared addr space

• Inter-Task Communication
• Shared data
• Mutual exclusion
• Semaphore
• Message queue
• Pipe
• Network facilities socket, RPC
• signal

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Basic OS Service of VxWorks (cont.)

• Memory Mgmt. (MM)
• Programmers responsibility to alloc stack for
  task
• Simple heap allocator First-Fit
• I/O system
• UNIX-like file/dir/device
• Buffered I/O stdio
• Formatted I/O printf(),
• POSIX AIO

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Basic OS Service of VxWorks (cont.)

• File System (FS)
• dosFs FAT12/FAT16/FAT32
• rawFs
• tapeFs
• cdromFs
• TSFS access file on host
• TrueFFS for Flash memory devices

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Network Support of VxWorks

• TCP/IP
• 802.1X
• IPSec IKE
• Learning bridge
• NAT/NAPT
• OSPF v2/v3
• Radius
• Firewall
• PPP

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Network Support of VxWorks (cont.)

• IPv4
• TCP/UDP
• ICMP
• IGMP v1/v2

• IPv6
• TCPv6/UDPv6
• ICMPv6
• Neighbor Discovery

(Network APP) DNS TFTP RIP FTP SNTP NFS FTP6
Proxy ARP MIB-II Telnet DHCP
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A Glance of VxWorks
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Board Support Package (BSP)
BSP boot code basic device driver
libarch.a libos.a libwind.a BSP
vxWorks
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sysLib.c The Framework of BSP

• HW driver initialization
• Mem/addr space/MMU/cache routines
• Bus interrupt mgmt. routines
• Clock/timer routines

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Boot code arch dependent

• Cache
• TLB
• GRs in CPU
• CP0s registers
• PLL
• DDR

• Watchdog
• Exception/Interrupt
• RTC
• GPIO

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Case Study 1 slow loop on SPI Flash
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Case Study 1 slow loop on SPI Flash (cont.)
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Case Study 1 slow loop on SPI Flash (cont.)
32 byte boundary
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Case Study 1 slow loop on SPI Flash (cont.)
32 byte boundary
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Case Study 1 slow loop on SPI Flash (cont.)
The straightforward way - padding
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Case Study 1 slow loop on SPI Flash (cont.)

• Deficiency of the straightforward way
• The loop must be kept LESS THAN 32 bytes
• Anytime you changed the boot code, youd have to
  inspect your code to ensure ALL loops are fitted
  into 32 bytes boundary. Thats absolutely BORING!

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Case Study 1 slow loop on SPI Flash (cont.)
My solution part 1
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Case Study 1 slow loop on SPI Flash (cont.)
My solution part 2
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Case Study 2 busy stuck of intr.
IP-QoS need high resolution timer
Sys clk
unused
Thats it
unused
CPU has 4 general purpose timer
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Case Study 2 busy stuck of intr. (cont.)

• GP timer 1
• Set up timer value (interval)
• Counting down to 0
• Generate timer intr.
• Reload

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Case Study 2 busy stuck of intr. (cont.)
0x0000BABE (delay)
Timer value reg.
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Case Study 2 busy stuck of intr. (cont.)

• Issue phenomenon
• System boot up
• LED blink
• UART output
• HALT. (No UART output No LED status change)

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Case Study 2 busy stuck of intr. (cont.)
The reason under the iceberg
Timer value reg.
Reload
Timer reload value reg.
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Case Study 2 busy stuck of intr. (cont.)
How to fix
Timer value reg.
0x0000BABE (delay)
0xFFFFFFFF (about 21s)
Timer reload value reg.
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Case Study 3 load delay slot on MIPS R3000
The red dot denote a breakpoint settled by an
ICE debugger
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Case Study 3 load delay slot on MIPS R3000
(cont.)
(see MIPS run, 2ed, pp. 28)
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Case Study 3 load delay slot on MIPS R3000
(cont.)
The fix
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Case Study 4 stochastically stuck when jumping
to VxWorks
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Case Study 4 stochastically stuck when jumping
to VxWorks
ltpseudo code snippet 1gt Decompress(compressed
vxWorks image on Flash, RAM to hold decompressed
vxWorks image) Jump to decompressed vxWorks
entry point
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Case Study 4 stochastically stuck when jumping
to VxWorks (cont.)
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Case Study 4 stochastically stuck when jumping
to VxWorks (cont.)
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Case Study 4 stochastically stuck when jumping
to VxWorks (cont.)
ltpseudo code snippet 2gt Decompress(compressed
vxWorks image on Flash, RAM to hold decompressed
vxWorks image) Flush data cache Invalidate
instruction cache Jump to decompressed vxWorks
entry point
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Case Study 5 stochastically soft-reboot failure
due to PLL switch
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Case Study 5 stochastically soft-reboot failure
due to PLL switch (cont.)

• Set up PLL and then switch
• Fail in 1/20 1/10

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Atheros solution increase PLL output gradually
(25MHz -gt 150MHz -gt 400MHz)
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My solution Enable watchdog Switch PLL to
400MHz Disable watchdog
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Case Study 5 stochastically soft-reboot failure
due to PLL switch (cont.)
HW teams solution
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Thats all
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Importance of BSP
Availability Reliability Stability Performance
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Things BSP engineer need to know

• Arch Inst., Pipeline, cache, exception/interrupt
• Mem SDRAM, DDR, NOR/NAND
• Bus UART, JTAG, SPI
• Misc PLL, Timer, GPIO, watchdog, DMA
• OS toolchain
• Debugging tool ICE, debugger

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Ad one
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Ad two
TP-LINK is hiring!
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The End
QA