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1
A 20/30 Gbps CMOS Backplane Driver with Digital
Pre-emphasis

• Paul Westergaard, Timothy Dickson, and Sorin
  Voinigescu
• University of Toronto
• Canada

2
Outline

• Motivation
• Design Goals
• Circuit Description and Design
• Experimental Results
• Summary and Conclusion

3
Motivation

• Application
• Serial inter-chip communications over backplanes
  at 20-Gb/s.
• Unfulfilled Needs
• CMOS implementation over 10-Gbps
• gt 30 dB dynamic range, low-power
• Programmable width and height pre-emphasis to
  increase receiver simplicity
• Prior Art
• Previous CMOS backplane drivers have only
  achieved 10 Gb/s data rate.

4
Design Goals

• 30-Gb/s main path operation without pre-emphasis
• 20-Gb/s fully featured operation with
• digital pre-emphasis
• eye-crossing
• output swing control
• High Sensitivity (lt10 mVpp per side)
• Large output swing (gt350 mVpp per side)
• 50-Ohm input/output matching
• 1.5 V supply
• 130 nm CMOS implementation

5
Circuit Design and Description
6
Biasing for peak fT and NFMIN

• Peak fT bias
• 0.3mA/um
• Min. NFMIN
• 0.15mA/um

Multi-stage amplifiers with signal path
transistors biased at half peak fT
7
Circuit Architecture

• Multi-stage amplifier implementation
• Input stage biased and sized for high gain and
  low noise
• Inductive broad-banding in every inverter stage
  to reduce power and increase speed
• Main (higher-speed) and pre-emphasis paths are
  parallelized

8
Block Diagram
9
Input Matching and Low-Noise Comparator
10
Eye-crossing Control
D. S. McPherson, S. Voinigescu et al IEEE GaAs
IC Symp. - Oct. 2002
11
Digital Pre-emphasis Delay Circuit
12
Digital Differentiator
13
Inductor design considerations

• Inductor broadband 2-p model model extracted
  for design from ASITIC simulations.
• Multi-layer ( 2 or 3 metals) design used to
  minimize inductor area (400, 700, 900 pH used)
• Largest inductor side is 44 um (900 pH)

14
Experimental Results
15
Chip Photograph
16
Input/Output Return Loss
17
Measured Eye-diagrams 0.3Vp-p output
25 Gb/s
20 Gb/s
30 Gb/s
18
Sensitivity
Input 21mVpp one side onlyOutput 80mVpp
per side
20 Gb/s
30 Gb/s
19
20-Gbs Eye with Pre-emphasis
20
Output Swing Control _at_20Gbps
Input 200mVpp one side only
Output 170mVpp
Output 340mVpp
21
Output Swing Control _at_30 Gbps
Input 200mVpp one side only
Output 170mVpp
Output 270mVpp (Gain at 30 Gb/s!)
22
30-70 Crossing Control _at_20 Gbs
50
70
30
23
40-60 Crossing Control _at_ 25 Gbs
50
60
40
24
Summary and Conclusion
25
Performance Summary
Parameter Measured val.
Technology 130nm CMOS
Supply Voltage 1.5 V
Power Dissipation 150 mW
Output Swing _at_ 20 Gb/s 170-350 mVp-p
Pre-emphasis _at_ 20 Gb/s 30/10
Crossing Control _at_ 20Gb/s 30 to 70
Eye sensitivity _at_ 20 Gb/s 20(10) mVpp
Dynamic Range _at_ 20 Gb/s 30 dB
Noise Figure(10GHz,15GHz) 16.5 dB, 17 dB
S11/S22 up to 50 GHz lt-12 dB
26
Conclusion

• First CMOS driver above 20 Gb/s
• Novel digital pre-emphasis
• High sensitivity, dynamic range
• Large output swing
• Eye-crossing control
• Communications between chips and backplanes is
  feasible at 20 Gb/s in 130-nm CMOS technology

27
Acknowledgements

• Rudy Beerkens and Boris Prokes of
  STMicroelectronics Ottawa
• STMicroelectronics for fabrication
• Micronet and Gennum Corporation for financial
  support
• Quake Technologies for access to 40 Gb/s BERT