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A Design Environment for High Throughput, Low
Power Dedicated Signal Processing Systems
W. Rhett Davis, Ning Zhang, Kevin Camera, Fred
Chen, Dejan Markovic, Nathan Chan, Borivoje
Nikolic, Robert W. Brodersen University of
California at Berkeley Berkeley Wireless
Research Center
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Outline of Presentation

• Benefits of Direct Mapping
• Standard DSP-ASIC Flow
• Chip-in-a-Day Flow
• Enabling Factors
• Design Examples
• Conclusion

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Direct Mapping Minimizes Power
Flexibility
Efficiency
100x-1000x Difference in Power
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Direct Mapping for Wireless Algorithms

• Low processing rates (wireless baseband 25
  Msps)
• High Complexity
• Low Power

P ? f ? C ? VDD2
Use low VDD / parallelism
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Standard DSP-ASIC Design Flow
Problems

• Separation of engineering teams makes exploration
  hard
• Uncontrolled looping when pipeline stalls
• Feedback to system designer is an aberration, but
  should be encouraged

Prohibitively Long Design Time for Direct Mapped
Architectures
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Direct Mapping Design Flow

• Encourages iterations of layout
• Controls looping
• Reduces the flow to a single phase
• Depends on fast automation

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Outline of Presentation

• Benefits of Direct Mapping
• Standard DSP-ASIC Flow
• Chip-in-a-Day Flow
• Enabling Factors
• Design Examples
• Conclusion

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Capturing Design Decisions

• Categories
• Function - basic input-output behavior
• Signal - physical signals and types
• Circuit - transistors
• Floorplan - physical positions

How to get layout and performance estimates in a
day?
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Automated Design Flow

• New Software
• Generation of netlists from Simulink
• Merging of floorplan from last iteration
• Automatic routing and performance analysis
• Automation of flow as a dependency graph (UNIX
  MAKE program)

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Why Simulink?

• Simulink is an easy sell to algorithm developers
• Closely integrated with popular system design
  tool Matlab
• Successfully models digital and analog circuits

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Simulink Models Datapath Logic

• Dataflow primitives(parallelism)
• Fixed-Point Types
• Completely specify function and signal decisions
• No need for RTL

Multiply / Accumulate
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Stateflow Models Control Logic

• Extended finite state-machine editor
• Co-simulation with Simulink
• New SoftwareStateflow-VHDL translator
• More complete capture of function decisions

Address Generator / MAC Reset
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Specifying Circuit Decisions
Time-Multiplexed FIR Filter

• Macro choices embedded in Simulink
• Cross-check simulations required

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Hierarchy Hardened Progressively

• Macro characterization saved for fast estimates
• Each level of hierarchy becomes a new hard macro
• Higher levels of hierarchy are adjusted
• When top level of hierarchy is hardened, the
  design is done

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Capturing Floorplan Decisions

• Commercial physical design tools used
• Instance names in floorplan match Simulink
• Placements merged on each iteration
• Manhattan distance can be used for parasitic
  estimates

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Outline of Presentation

• Benefits of Direct Mapping
• Standard DSP-ASIC Flow
• Chip-in-a-Day Flow
• Enabling Factors
• Design Examples
• Conclusion

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Reduced Impact of Interconnect

• 2X inverter
• 0.25 mm
• 1 mm isolated metal 1 wire

Long wires can be modeled as lumped capacitances
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Race-Immune Clock Tree Synthesis

• Race margin 580 ps
• 0.18 mm
• VDD 1 V

Currently supports 1M transistor designs
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Outline of Presentation

• Benefits of Direct Mapping
• Standard DSP-ASIC Flow
• Chip-in-a-Day Flow
• Enabling Factors
• Design Examples
• Conclusion

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Example 1 Macro Hardening
Most time/disk space spent on extraction and
power simulation
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Example 2 Test Chip

• 300k transistors
• 0.25 mm
• 1.0 V
• 25 MHz
• 6.8 mm2
• 14 mW
• 2 phase clock
• 3 layers of PR hierarchy

Parallel Pipelined FIR Filter(8X decimation
filter for 12-bit 200 MHz SD)
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Example 3 CDMA Baseband Receiver

• 500k transistors
• 0.18 mm
• 1.0 V
• 25 MHz
• 1.1 mm2
• 21 mW
• single phase clock
• 5 clock domains
• 2 layers of PR hierarchy

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Conclusion

• Design flows should encourage system designers to
  explore design space by creating layout
• Design phases should be determined by hierarchy
  hardening, not separation of expertise
• Low supply voltages make delay estimates easier,
  simplify design flow
• Chip layout in a day is feasible - Simulink
  netlist generation - Floorplan merge -
  Dependency graph automation - Characterization -
  Simulink / VHDL translation - Clock Tree Synth.