Overview of Lecture

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Overview of Lecture

• Features of 68HC11
• Programmers model of 68HC11
• 68HC11 registers
• Instructions set
• Simple assembly programs

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Features of MC68HC11

• First Developed by Motorola in 1986
• MC86HC11 is an 8-bit microcontroller
• 8-bit CPU
• On-chip memory, I/O ports and A/D converter
• It has an 8-bit data bus and 16-bit address bus

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Features of 68HC11 cont

• 256 bytes SRAM
• 512 bytes EEPROM
• 8 KB ROM
• 3 input capture channels
• 5 output compare functions
• one serial communication interface (SCI)
• one serial peripheral interface (SPI)
• 8-channel 8-bit A/D converter
• watchdog system

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Examples of microcontroller applications - Displa
ys - Printers - Keyboards - Modems - Charge card
phones - Washing machines - Microwave
ovens - Automobile engine fuel injection - Fax
machines - Motor speed control
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Programmers model

• Programmers model includes 7 registers available
  to user - Accumulators A and B, index registers X
  and Y, PC, SP, condition code register CCR
• 16-bit D accumulator comprising A and B enables
  16-bit operations - D is not counted as a
  separate register
• 6 addressing modes of handling data to speed up
  processing and/or reduce number of instruction

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68HC11 registers

• Two categories of Register
• I/O Registers -
• CPU Registers
• I/O Registers
• control operation of I/0 subsystems
• record status of I/O subsystem
• treated as memory locations when accessed
• CPU registers
• used to perform general purpose operations

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MC68HC11 CPU Registers
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MC68HC11 CPU Registers cont

• General Purpose accumulators A and B
• Both A and B are 8-bit registers. Most
  arithmetic functions are performed on these two
  registers. The two accumulators can be cascaded
  to form a single 16-bit accumulator which is
  referred to as the D accumulator.
• Index Registers IX and IY
• These two registers are used mainly in addressing
  memory operands. However they are used in some
  other applications as well.

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MC68HC11 CPU Registers cont..

• Program Counter (PC)
• This is a 16-bit register which specifies the
  address of the next instruction to be executed.
  The CPU fetches instruction one byte at a time
  and increments the PC by 1 after fetching each
  instruction byte.
• Stack Pointer (SP)
• The stack is a temporary storage area in memory
  which is used by the system to store information
  during interrupts and subroutine calls. SP is a
  16-bit register which points to the address of
  next free location at the top of the stack. The
  stack operates on a first-in-last-out principle.

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MC68HC11 CPU Registers cont..

• Condition Code Register (CCR)
• This 8-bit register is used to keep track of the
  program execution status, control the execution
  of conditional branch instructions and
  enable/disable interrupt handling. It contains
  five code condition indicators (C, V, Z, N and H)
  two interrupt masks (I and X) and a stop disable
  bit (S).
• Various instructions have an effect on these
  indicators and thus give an indication of the
  status of ALU operation.
• They can be accessed by a programmer for branch
  and conditional statements.

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CCR cont
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Condition Code Register (CCR)

• Carry/Borrow (C)
• C bit is set (set to 1) if a carry or borrow
  occurs after an ALU operation. C bit also acts
  as an error flag for multiply and divide
  operations. Shift and rotate operations operate
  with and through the carry bit to facilitate
  multiple-word shift operations.
• Overflow (V)
• Overflow bit is set if an operation causes an
  arithmetic overflow. Otherwise the V bit is
  cleared (set to 0).
• Zero (Z)
• Z bit is set if the result of an arithmetic,
  logic, or data manipulation operation is zero.
  Otherwise the Z bit is 0.

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Condition Code Register (CCR) cont..

• Negative (N)
• N bit is set if the result of an arithmetic,
  logic, or data manipulation operation is
  negative. Otherwise the N bit is 0. Left most bit
  is MSB called sign bit. If MSB 1, value is
  negative and if MSB 0, value is positive.
• Half Carry (H)
• Half carry flag is used for BCD arithmetic. H
  flag is updated by three instructions ABA, ADD,
  and ADC. H bit is set when a carry occurs from
  bit 3 to bit 4 during BCD addition.

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Binary coded decimal arithmetic

• 44 BCD 0 1 0 0 0 1 0 0
• 23 BCD 0 0 1 0 0 0 1 1
• 67BCD 0 0 1 1 0 0 0 1 1 1

Half carry
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Condition Code Register (CCR) cont..

• I Interrupt Mask (I)
• I bit is the interrupt request (IRQ) bit
  disables all maskable interrupts. If I set, CPU
  will not recognize interrupts and continue normal
  execution. When an interrupts occurs - I bit is
  set to 0, CPU recognize interrupt and CPU
  registers are placed on stack.
• X Interrupt Mask (X)
• X bit disables interrupts from the XIRQ pin.
  After any reset, X is set by default and must be
  cleared by a software instruction.
• Stop Disable (S)
• S bit is STOP bit allows or disallows STOP
  instruction. If CPU encounters a STOP instruction
  while S bit is set, it is treated as no-operation
  (NOP). S is set by reset i.e. STOP disabled by
  default.

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Data Types

• The 68HC11 supports the following data types
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
• A Byte is eight bits wide
• A word is two consecutive bytes and the most
  significant byte is stored at the lower value
  address

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Instructions set

• MC68HC11 uses 8-bit op-codes
• Potentially only 256 (28) instructions
• Note each instruction has a number of variants
  due to addressing modes (next week)
• Additional instructions are available due to an
  additional byte called a prebyte.

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Instructions set cont

• Data transfer
• Arithmetic
• Logical
• Bit manipulation
• Shift and rotate
• Branch and jump
• Subroutine call
• Interrupt handling
• Miscellaneous

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Data transfer instructions

• Load, Store and Transfer instructions
• Examples
• LDAA C100 load accumulator A with contents
  of memory location C100
• LDAB 50 load accumulator B with value
  50hex
• STAA C724 store value of A in memory
  location C724
• TBA transfer contents of B
  into A

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ADD instruction performs addition

• ABA A ? AB
• ADDA ltoprgt A ? AM or A ? Avalue
• ADDB ltoprgt A ? BM or B ? Bvalue
• ADDD ltoprgt D ? DMM1 or D ?
  Dvalue(16-bit)
• ltoprgt is specified using immediate, direct,
  extended, or index mode
• Examples.
• ADDA 10 A ? A10
• ADDA 20 A ? A0020
• ADDD 30 D ? D00300031

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SUB instruction performs subtraction

• SBA A ? A-B
• SUBA ltoprgt A ? A-M or val
• SUBB ltoprgt B ? B-M or val
• SUBD ltoprgt D ? D-MM1 or val
• SBCA ltoprgt A ? A M C flag
• SBCB ltoprgt A ? B M C flag
• ltoprgt can be immediate, direct, extended, or
  index mode
• Examples
• SUBA 10
• SUBA 10
• SUBA 0,X
• SUBD 10,X

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Example program

• Add two numbers using only accumulator A and
  store the result in memory location 1064

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Memory Addressing
Figure 1.5 Data transfer between CPU and memory
The 68HC11 can address up to 16 signal lines i.e.
up to 216 (65536) different memory
locations. Memory Space is from 0000h to
FFFFh 64K of memory (1K1024) - each location
stores 1 byte
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Summary

• Introduction to the 68HC11 architecture
• Overview of the internal structure and
  architecture of the 68HC11
• The 68HC11 registers
• Code condition Register
• Data transfer instructions and example program
• Memory addressing