Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation

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Analytical Thermal Placementfor VLSI Lifetime
Improvement and Minimum Performance Variation
Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao
Liu UC San Diego UC Santa Cruz
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Outline

• Background
• Modeling and Theoretical Results
• Analytical Thermal Placement
• Experiment
• Summary

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VLSI On-Chip Temperature Scaling
Courtesy, Intel
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Temperature Scaling Why and How

• Scaling has led to temperature rise in VLSI
• Higher integration
• Higher clock frequency
• Leakage power
• Cooling techniques are stagnant
• Air ventilation
• Liquid cooling
• Low power design
• Power gating, clock gating, dynamic scheduling
• Placement

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Chip Packaging Structures

• Heat dissipation through bulk silicon in wire
  bond packaging

• Devices and interconnects closer to heat sinks in
  flip chip packaging

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Heat Dissipation Equations

• Dynamic

• Static

• From Boltzmanns Equation
• p ( r ) power density
• g ( r ) thermal conductivity

• Poissions Equation

• Purely Resistive Network

• Electrical analogue RC Circuit
• Thermal conductance G
• Heat capacity C

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Thermal Effects on Performance

• Higher temperature ?
• Superlinear decrease of carrier mobility
• Linear decrease of transistor threshold voltage
• Increase or decrease of transistor output current
  depending on transistor threshold voltage, supply
  voltage, etc.
• Increase of interconnect resistance

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Thermal Effects on Circuit Lifetime

• Circuit lifetime Tf decreases superlinearly with
  rising temperature
• Hot carriers
• Oxide breakdown
• Electromigration
• where
• J current density
• Q activation energy (1.0eV for copper)
• k Boltzmann constant
• T temperature
• D given by device structure

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Previous Thermal Placers

• Objective
• Total on-chip temperature1
• Maximum on-chip temperature23
• Method
• Simulated annealing34
• Min-cut bi-partition1
• Thermal simulation
• Compute thermal resistance matrix at each
  iteration134

• Chao and Wong, Thermal placement for high
  performance multichip modules, ICCD, 1995
• Chu and Wong, A matrix synthesis approach to
  thermal placement, ISPD, 1997
• Cong, Wei, and Zhang, A thermal-driven
  floorplanning algorithm for 3D IC, ICCD, 2004.
• Tsai and Kang, Cell-level placement on improving
  substrate thermal distribution, IEEE Trans. CAD,
  2000

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Outline

• Background
• Modeling and Theoretical Results
• Analytical Thermal Placement
• Experiment
• Summary

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Thermal Modeling

• ? FDM (Finite Difference Method)
• ? MOR (Model Order Reduction)
• ?

Heat source
Boundary thermal resistor
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Objective and Complexity

• Placement for minimum on-chip temperature at a
  specific spot is linear
• How to locate current sources s.t. Vo is
  minimized?
• Solved by greedy algorithm
• Locate maximum current source with minimum
  resistance

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Objective and Complexity

• Placement for minimum average on-chip temperature
  is linear
• How to locate current sources s.t. SiVi is
  minimized?
• Solved by greedy algorithm
• Locate maximum current source with minimum
  resistance

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Objective and Complexity

• Placement for minimum maximum on-chip temperature
  is NP-hard
• Reduces to the bi-partition problem
• Given
• we have

i1,2 and i,j on the same side
otherwise
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Outline

• Background
• Modeling and Theoretical Results
• Analytical Thermal Placement
• Experiment
• Summary

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Problem Formulation

• Given
• Chip dimensions 0ltxlta, 0ltyltb, 0ltzltd
• Thermal parameters
• Thermal conductivity k on chip top
• Thermal conductivity kN on chip bottom
• Effective heat transfer coefficient h on chip
  bottom
• Ambient temperature Tr
• Cells C of power consumption P
• Netlist N
• Find a cell placement which minimizes sum of
  total wirelength and maximum temperature

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Analytical Placement

• Approximate the NP-hard placement problem as a
  nonlinear optimization problem
• Relax the non-overlapping constraint into a cell
  density unevenness penalty function
• Minimize

relax
legalize
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Cell Density Distribution

• A cell centered at (xc,yc) of width w and height
  h distributes its area over a grid of points
  (x,y)
• where

Cell density
Cell density
1
1
r
-r/2
r/2
x
-r/2
x
r/2
-r
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Smooth Wirelength Function

• Half perimeter wirelength
• Approximate min/max by logarithm of sum of
  exponents

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Analytical Thermal Placement

• Minimize
• where

• A, b, g are such that terms are comparative
• G-1 does not change during placement iteration

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Congestion Penalty Function

• Minimize
• where

• If congested sharper increase of penalty ?
  stricter enhancement
• If not congested no penalty ? more relaxed

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Outline

• Background
• Modeling and Theoretical Results
• Analytical Thermal Placement
• Experiment
• Summary

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Experiment Setting

• We compare analytical thermal placement to
  thermal effect oblivious analytical placement
  APlace
• Two industry design test cases of gate array
  logic in 130nm and 180nm technologies

Utilization
Total Power
Technology
rows
blocks
cells
design
0.60
10.0W
130nm
129
0
13397
I
0.43
10.0W
180nm
251
5
7128
II
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Thermal Placement Data Flow
Chip Dimensions Material, Boundary Conditions
Netlist
Thermal Simulation
Power Profile
Thermal Resistances
Analytical Thermal Placement
Temperature Reduction
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A Snapshot of Placement Result
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Analytical Thermal Placement vs. Traditional
Analytical Placement
Test case I 130nm industry design of13K
cells
Placer
HPWL CPU
Max Temp
g
(s)
()
(mm)
()
(K)
APlace
250.15
100.00
504.80
100.00
12.10
0.00
ATP
718.53
92.19
465.35
97.47
11.33
0.00
636.13
92.47
466.78
92.23
11.16
0.02
800.52
95.39
481.54
82.15
9.94
0.10
Test case II 180mm industry design of 7K
cells
Placer
HPWL CPU
Max Temp
g
(s)
()
(mm)
()
(K)
APlace
211.37
100.00
923.55
100.00
2.73
0.00
ATP
204.94
98.06
905.62
109.52
2.99
0.00
496.91
98.03
905.34
99.63
2.72
0.02
507.94
99.55
919.42
69.23
1.89
0.10
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Outline

• Background
• Modeling and Theoretical Results
• Analytical Thermal Placement
• Experiment
• Summary

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Summary

• We propose analytical thermal placement and
  achieve 17.85 and 30.77 maximum on-chip
  temperature variation reduction and 4.61 and
  0.45 wirelength reduction compared with the
  existing analytical placement for the two
  industry designs, respectively
• We present theoretical results on the complexity
  of specific spot temperature, average on-chip
  temperature, and maximum on-chip temperature
  minimum placement as linear, linear, and NP-hard
• Future directions
• Thermal effect aware performance optimization
• 3-D thermal placement

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Thanks for your attention!