Built-In Self-Test for Field Programmable Gate Arrays funded by National Security Agency

1
Built-In Self-Test for Field Programmable Gate
Arraysfunded by National Security Agency

• Chuck Stroud
• Electrical Computer Engineering
• Auburn University

2
Outline of Presentation

• Overview
• Built-In Self-Test (BIST)
• Field Programmable Gate Arrays (FPGAs)
• BIST for FPGAs
• Logic resources
• Routing resources
• Demonstration of FPGA logic BIST Diagnosis

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The Need for Test

• 2000 International Technology Roadmap for
  Semiconductors (by the Semiconductor Industry
  Association - SEMATECH) predicts by 2014
• Test machines will cost gt 20M
• It will cost more to test a transistor than to
  manufacture it
• Built-In Self-Test (BIST) is a likely solution
• Analog BIST is needed for mixed-signal systems
• Fault diagnosis is needed with BIST
• Tools are needed for automating BIST

4
What is BIST?

• Basic idea Add circuitry to IC or PCB to
  facilitate testing itself
• Only power and clock needed during BIST sequence
• Pass/Fail result reported at end of BIST sequence
• No need for external test equipment
• Necessary components
• Test Pattern Generator (TPG)
• Output Response Analyzer (ORA)
• For system level use
• Test controller
• Input isolation
• Penalties area overhead, performance
• Benefits low testing time cost

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Overview of FPGAs

• Configuration Memory
• Programmable Logic Blocks (PLBs)
• Programmable Input/Output Cells
• Programmable Interconnect

Typical Complexity 5M - 100M transistors
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Basic FPGA Operation

• Load Configuration Memory
• Defines system function
• Input/Output Cells
• Logic in PLBs
• Connections between PLBs I/O cells
• Changing configuration memory gt changes system
  function
• Can change at anytime
• Even while system function is in operation
• Run-time reconfiguration (RTR)

11100110100010001001010100010111000101001010101010
01001000100010101001001001100100100001111000110010
10001000011001000101000100100100100010100101010100
10010010100010100101000101001010010001001010101110
10101010101010101010101111011111000000000000001101
00111110000100111000001110010010100000000111110010
01000101001110010010100001111000111000100101010101
01010101010010100101010100100101010101010101001001
001
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Programmable Logic Blocks

• PLBs can perform any logic function
• Look-Up Tables (LUTs)
• Combinational logic
• Memory (RAM)
• Flip-flops
• Sequential logic
• Special logic
• Add, subtract, multiply
• Count up and/or down
• Dual port RAM
• Must be tested in all modes of operation
• PLBs/FPGA 100 to 50,000

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Programmable Interconnect

• Wire segments Programmable Interconnect Points
  (PIPs)
• cross-point PIPs connect/disconnect wire
  segments
• To turn corners
• break-point PIPs connect/disconnect wire
  segments
• To make long and short signal routes
• multiplexer (MUX) PIPs select 1 of many wires for
  output
• Used at PLB inputs
• Primary interconnect media for new FPGAs

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BIST for FPGAs

• Basic idea reprogram FPGA to test itself
• BIST logic disappears after test
• No area overhead or performance penalties
• Applicable to all levels of testing
• A generic test for a generic component
• Independent of system function
• Good diagnostic resolution
• Logic Look-Up Table (LUT) or flip-flop
• Routing wire segment or switch
• Reconfigure system function for fault-tolerance
• Cost memory to store BIST configurations

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BIST Architecture for PLBs

• Configure row (or columns) of PLBs as
• Test Pattern Generators (TPGs)
• Output Response Analyzers (ORAs)
• Blocks Under Test (BUTs)
• Reverse rolls after testing 1st set of BUTs

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Diagnostic Procedure
MULTIple faulty CELL LOcator MULTICELLO

• Step 1 Record ORA results

Step 2 Mark known good BUTs
Step 3 Mark implied good BUTs
Step 4 Mark known faulty BUTs
Step 5 Look for inconsistences gt implies
possible interconnect faults
Step 6 If every PLB has been identified as
fault-free or faulty, the group of faulty PLBs
has been uniquely diagnosed gt otherwise mark
as unknown
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Routing BIST Architecture

• Wires Under Test (WUTs)
• Wire segments connected via PIPs PLBs to form
  WUTs
• Opposite values on busses not under test (PIPs
  stuck-on)
• All WUTs are 2-tested to detect equivalent faults
• TPGs ORAs formed as in logic BIST
• Exhaustive test patterns detect shorts, opens,
  stuck-at faults
• ORA compares two sets of WUTs (A WUTs B WUTs)

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Routing BIST Architecture

• Uses small Self-Test AReas (STARs) to test
  routing resources
• Good diagnostic resolution
• To STAR
• Higher speed testing
• Fewer series PIPs delays
• Run STARs in parallel
• V-STARs test vertical routing
• H-STARs test horizontal routing

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Diagnostic Configurations

• Partition into smaller STARs
• Identify faulty region of WUT

• Add ORAs change directions
• Identify fault region of WUT

ORA

• Re-route portions of net
• Identify faulty wire segment or PIP

ORA
ORA
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Test Results for Faulty FPGAs

• Failures from Chip 2
• At least 2 faults
• maybe at intersection of STARs

• Failures from Chip 1
• At least 1 fault
• maybe at intersection of STARs

• Diagnostic results
• A short at row 1 column 12
• Short in 3 wires of 4-wire bus
• row 5 columns 6-8

• Diagnostic results
• A short at row 10 column 8

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Fault Injection Emulator

• Faulty FPGA are difficult to find
• 1 FPGA with faulty PLB 2 FPGAs with faulty
  routing
• We created a Fault Injection Emulator
• Intercepts modifies configuration bits prior to
  download
• Fault Emulator can create multiple faults in
• PLBs LUTs, flip-flops, etc.
• Interconnect PIPs stuck-on stuck-off

1101 1001 0001
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BIST Demonstration

• Graphic User Interface
• Shows what is happening inside FPGA during test
• Provides interface to fault injection emulation
• Fault Injection Emulator
• Inserts faults into configuration data file
• Emulated faults are downloaded with BIST phases
• Logic BIST
• MULTICELLO diagnostic algorithm incorporated
• Current demo for Xilinx 4010XL FPGA
• 20x20 PLB array with 100K PIPs 25K wire
  segments
• BIST phases automatically generated for any 4000
  series FPGA by programs we have developed