Test Planning for the Effective Utilization of PortScalable Testers for Hetrogeneous CoreBased SOCs

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Test Planning for the Effective Utilization of
Port-Scalable Testers for Hetrogeneous Core-Based
SOCs
Anuja Sehgal Krishnendu Chakrabarty
Electrical and Computer EngineeringPratt School
of EngineeringDuke University
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Motivation

• Increased SOC complexity
• Embedded cores in multiple clock domains
• Integration of cores from different generations
• Testing at different scan frequencies
• Current generation ATEs equipped with
  port-scalability
• Match ATE channel frequencies to different scan
  data rates for the embedded cores

ATE
SOC
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Current-Generation ATEs

• Port scalability features
• Simultaneously drive different channels at
  different data rates
• Digital speeds of upto 2.5 Gbps
• Application flexibility
• Number of tester channels with high data rate
  limited

Agilent
Teradyne
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Modular Testing of SOCs

• Test access mechanisms (TAMs) impact testing
  time, test cost, power and routing
• Test wrappers translate test data supplied by
  TAMs
• TAM optimization and test scheduling are critical

SOC
ATE
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Selection of Data Rate for a Core
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Test Access Architectures for Heterogeneous SOCs
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Test Access Architectures for Heterogeneous SOCs
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Test Access Architectures for Heterogeneous SOCs
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Test Access Architectures for Heterogeneous SOCs
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Test Access Architectures for Heterogeneous SOCs
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Problem Statement

• Given
• Test data parameters for N embedded cores
• Maximum scan frequency fi for each core i
• SOC-level TAM width W

• Determine
• The number of TAM partitions B
• Width wj and scan frequency fj of each TAM
  partition j
• Assignment of cores to TAM partitions

• such that
• TAM frequency does not exceed the maximum scan
  frequency of any core assigned to that TAM
  partition
• The overall test time is minimized
• The sum of the widths of all the TAM partitions
  does not exceed W

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Problem Statement (Cont.)

• Ti(wj) Testing time of core i on TAM width wj
• Ti(wj, f) Testing time of core i at frequency
  f on TAM width wj
• Ti(wj, f) Ti(wj) / f
• Variable xij 1, if core i assigned to TAM
  partition j
• Testing time on TAM j is ?j Ti(wj) xij / fj

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Problem Statement (Cont.)

• Minimize T maxj ?j Ti(wj) xij / fj subject to

• ?j xij 1, every core connected to exactly one
  TAM partition
• ?j wj W, total TAM width is W
• fj minifi xij\0
• wj ? wmax, maximum width of any TAM partition is
  wmax

NP-hard problem
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Mathematical Programming Model

• Objective Min. T maxj ?j Ti(wj) xij tij
  subject to
• ?j xij 1
• ?j wj W
• wj ? wmax
• xij fij lt fi
• f1j f2j fNj .

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Lower Bound Calculation

• Given collection of rectangles for the cores
• Select one rectangle for each core
• Pack rectangles into a bin of fixed height
• Such that bin width is minimized

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Lower Bound Calculation

• Ri(w,f) Area of rectangle representing Core i
  tested at TAM width w
• Ri(w, f) w ? Ti(w, f) , f ? f i
• Minimum area rectangle Rimin(w, f)
• Minimum area rectangle is of height 1 and test
  time Ti(1, f i), i.e.,
• Rimin(w, f) Ti(1, f i)

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Lower Bound Calculation

• T W
• R1(1, f1) R2(1, f2)
  RN(1, fN )

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Optimization Procedure
Iterative descent procedures
Initialize TAM partitions
Split TAMs
wj, fj
Core Shuffle
Assign Cores
Initial SOC testing time
Merge TAMs
Redistribute TAMS
O(B2max N N log2N)
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Split_TAMs Procedure
Initial testing time
Core 1 (f1100)
Core 2 (f250)
Core 3 (f3100)
TAM A (f 50)
TAM B (f80)
TAM C (f120)
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Core_shuffle Procedure
Initial testing time
Core 1 (f1100)
Core 2 (f2120)
Core 3 (f3100)
TAM A (f 100)
TAM B (f80)
TAM C (f120)
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Redistribute_TAMs Procedure
Initial testing time
TAM A (f 100)
TAM B (f 120)
TAM C (f 80)
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Redistribute_TAMs Procedure
Initial testing time
TAM A (f 100)
Freed TAM wires
TAM B (f 120)
TAM C (f 80)
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Redistribute_TAMs Procedure
Initial testing time
TAM A (f 100)
TAM B (f 120)
TAM C (f 80)
New testing time
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Merge_TAMs Procedure
Initial testing time
TAM A (f 100)
Core 2
Core 3
Core 1
TAM B (f 120)
Core 4
Core 5
TAM C (f 80)
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Merge_TAMs Procedure
Initial testing time
TAM A (f 100)
Core 1
Core 2
Core 3
Core 4
Core 5
TAM C (f 80)
New testing time
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Comparison with Baseline
p22810 (5 frequencies 10 to 50 MHz)
Test time (µs)
37
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Comparison with Baseline
p34392 (9 frequencies 40 to 200 MHz)
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Test time (µs)
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Comparison with ILP and Baseline
d695 (2 frequencies 40 MHz and 50 MHz)
0
Test time (µs)
0
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Comparison with ILP and Baseline
a586710 (2 frequencies 40 MHz and 50 MHz)
Test time (µs)
0
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Conclusions

• We have presented a new test planning technique
  for core-based SOCs
• Exploits port-scalability features of testers
• Match ATE channel rates to scan data rates
• Heuristic method is scalable with multiple scan
  data rates
• Heuristic method performs significantly better
  than the baseline case
• Close to optimal results and near lower bounds