An EnergyAware Architectural Exploration Tool for ARMbased SOCs

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An Energy-Aware Architectural Exploration Tool
for ARM-based SOCs

• Dan Crisu, Sorin Cotofana, and Stamatis
  Vassiliadis
• Computer Engineering Laboratory
• Electrical Engineering Department
• Delft University of Technology

2
Summary

• Introduction
• Problem statement
• The proposed power-aware design exploration
  framework
• Datapath power models
• Experimental validation of the tool
• Conclusions

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Introduction

• Motivation for low-power design

• battery-operated electronics

• packaging and cooling costs

• reliability concerns

• We need

TIME-POWER-AREA (TPA) implementation
space exploration
4
Introduction

• Where is power estimation more effective?

• Circuit- and gate-level
• power available late
• factor of 2 or less in power savings

• Algorithm- and architecture-level
• power available early
• factor of 10-100 or more in power savings

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Problem Statement

• ARM System-on-chip
• Low-power ARM CPU core
• High- and low-speed peripherals
• Memory
• AMBA bus

Problem to solve Coprocessor/peripheral unit
power consumption estimation at the architectural
level
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The Proposed Power-Aware Design Exploration
Framework
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The Proposed Power-Aware Design Exploration
Framework
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The Proposed Power-Aware Design Exploration
Framework

• Benefits of the proposed approach
• software/hardware experimental partitioning
  schemes
• performance monitoring (throughput, power
  consumption)
• environment to test new algorithms
• bit width precision tweaking

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Datapath Power Models

• Main reason for power consumption in contemporary
  digital logic
• charging/discharging capacitive nodes

Solution Power estimation at the architectural
level Dual Bit Type (DBT) data model (Landman 96)
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Datapath Power Models

• Dual Bit Type (DBT) data model
• library of hardware modules

• precharacterization (performed only once)
• circuit- or switch-level simulation with certain
  patterns
• builds a table (TC) per module of average
  effective capacitances per bit

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Experimental validation of the tool
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Experimental validation of the tool

• Library of hardware cells
• technology UMC 0.18 ?m 1.8V/3.3V 1P6M GENERICII
• precharacterization of a ripple-carry
  adder-subtractor employing HSPICE circuit
  simulator

Average capacitive coefficients per bit table for
the ripple-carry adder-subtractor
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Experimental validation of the tool
Simple coprocessor block diagram

• 9-bit microinstruction register
• Register file two-ported 16 -word by 8-bit
• ALU
• arithmetic ops
• logical ops

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Experimental validation of the tool
Simple coprocessor layout
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Experimental validation of the tool
Instruction trace A, B, C were generated using
biased noise generators
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Conclusions

• Power-aware ARMulator
• provides all the benefits of a co-design
  framework
• early power estimation
• power models accounts for signal activity, signal
  correlation and glitching
• less than 25 relative error compared with direct
  circuit-level simulation
• Ongoing research
• control, memory, and interconnect power models
  have still to be developed

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Author Contact Information
Dan CRISU
Sorin COTOFANA
Stamatis VASSILIADIS
E-mail dan, sorin, stamatis_at_ce.et.tudelft.nl
Computer Engineering Laboratory Electrical
Engineering Department Delft University of
Technology Mekelweg 4 (15th floor) 2628 CD
Delft The Netherlands Phone (31) 15
2783644 Fax [phone]
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Appendix - Datapath Power Models (1)
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Appendix - Datapath Power Models (2)
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Appendix - Datapath Power Models (3)
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Appendix - Datapath Power Models (4)

• Activity Model

- models activity, as well as physical
capacitance - computed using Dual Bit Type (DBT)
data model (Landman 96)

• Assumptions of the DBT data model
• data representation fixed-point
  twos-complement
• signal statistics stationary in time
• design logic style static logic

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Appendix - Datapath Power Models (5)
DBT Data Model a) Activity for positively and
negatively correlated waveforms b) Bit transition
activity for data streams with varying temporal
correlation
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Appendix - Datapath Power Models (6)
Templates for identifying data bit types
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Appendix - Datapath Power Models (7)
Transition templates for two-input modules
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Appendix - Datapath Power Models (8)
Resulting capacitive coefficients
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Appendix - Datapath Power Models (9)

• Library Characterization Method
• pattern generation input patterns for various
  UWN, and sign transitions are generated for the
  module being characterized
• simulation get the capacitance switched for
  these input activity patterns
• characterized for several complexity parameter
  values (e.g. word length, number of shift stages
  etc.)
• coefficient extraction the capacitance models
  are fit to the simulated capacitance data to
  produce a set of best fit capacitive
  coefficients
• The library precharacterization method is
  independent of the signal activity seen during
  the high level simulation !!

• Effective capacitance computation during
  simulation
• calculate breakpoints BP0 and BP1 for every data
  stream on the ports of the component from signal
  statistics (mean, variance, correlation) after
  the simulation
• the effective capacitance of an individual region
  (UWN, sign) of size Nr can be computed first by
  calculating what the capacitance would be if the
  region occupied all N bits of the module, then
  scale with Nr/N

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Appendix - Datapath Power Models (10)

• Formulas for breakpoints in the DBT data model

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Appendix - Datapath Power Models (11)

• Statistics