Experiment 7:Using Embedded Microcontroller Cores to Implement Complex Digital Systems

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Experiment 7Using Embedded Microcontroller Cores
to Implement Complex Digital Systems
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Experiment 7 Top level view of the implemented
circuit
FPGA
PIC µController
CLK
RESET
PORTC
PORTB
PORTA
7-Seg Decoder
Display
PORTA
3
PIC Microcontroller Core
MCLR
CLK
PROGRAM
PICROM 256 x 12
CONTROL UNIT
P C
8
Addr
Address Bus
Data
DATA
12
REGFILE
R8
Instruction Decoder
Fsel
8
4
8
R31
OPCODES
FSR
CONSTANTS
Din
Dout
W
ALU
Data Bus
8
4
8
8
EXTENDED ALU
COMPUTATIONS
PORTA
PORTB
PORTC
4
8
8
4
Flowchart of our PIC program
RESET
Set Port Directions
Sum lt 0 Counter lt 0
Wait for a rising edge at Port C(0)
Wait for a rising edge at Port C(0)
Port B lt Sum(3 downto 0)
N
Port B lt Port A Sum lt Sum Port A Counter lt
Counter 1
Wait for a rising edge at Port C(0)
Counter 8?
Y
Port B lt Sum(7 downto 4)
5
Selected Registers of PIC
ADDR
?
Working Register (Accumulator)
W
?
Program Counter
PC
PORTA
05
Bidirectional Input/Output Ports
PORTB
06
PORTC
07
08
R8
09
R9
R10
0A
Register File (General Purpose Registers)
. .
1E
R30
1F
R31
?
TRISA
Direction Registers for Ports A, B C
?
TRISB
?
TRISC
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Selected PIC Instructions (1)
MOVF f, d
MOVF f, 1
f
f ? lt8,31gt
MOVF f, 0
k ? lt0,255gt
W
MOVWF f
MOVLW k
W
k
MOVWF f
MOVLW k
f
W
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Selected PIC Instructions (2)
0
CLRF f
CLRF f
f
f ? lt8,31gt
0
CLRW
CLRW
W
8
Selected PIC Instructions (3)
INCF f, d
f
1
INCF f,1
INCF f,0
W
9
Selected PIC Instructions (4)
ADDWF f, d
W
f
ADDWF f, 1
ADDWF f, 0

10
Selected PIC Instructions (5)
ANDWF f, d
W
f
ANDWF f, 1
ANDWF f, 0
and
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Selected PIC Instructions (6)
SWAPF f, d
SWAPF f, 1
fH fL
SWAPF f, 0
W
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Selected PIC Instructions (7)
GOTO label
CALL label
RETLW
CALL label
CALL label
GOTO label
label
label
label
RETLW
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Selected PIC Instructions (8)
BTFSC f, b
f
7
b
0
f(b) 0?
BTFSC f, b
No
Next instruction
Yes
After-next Instruction
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Selected PIC Instructions (8)
BTFSS f, b
f
7
b
0
f(b) 1?
BTFSS f, b
No
Next instruction
Yes
After-next Instruction
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Selected PIC Instructions (9)
TRIS f
W
TRIS PORTA
TRIS PORTC
TRIS PORTB
1 Input port bit direction
0 Output port bit direction
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PIC Programming Environment
Source File in the PIC Assembly Language
.ASM
MPASM
.LST
.HEX
Listing File
HEX File
MPSIM
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Block RAMs in Spartan III FPGAs
Configurable Logic Blocks
I/O Blocks
Block RAMs
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Spartan-3 Block RAM Amounts
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Block RAM Port Aspect Ratios
used to implement PICROM 256x12
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Block RAM Port Aspect Ratios
1
2
4
0
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
81
0
2k x (81)
2047
162
0
1024 x (162)
1023
16,383
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Dual Port Block RAM
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Dual-Port RAM 1024 x 18
RAMB4_S4_S16
WEA
Port A Out 18-Bit Width
Port A In 1K-Bit Depth
ENA
RSTA
DOA170
CLKA
ADDRA90
DIA170
WEB
Port B Out 18-Bit Width
Port B In 1k-Bit Depth
ENB
RSTB
DOB170
CLKB
ADDRB90
DIB170

• Each port can be configured with a different data
  bus width
• Provides easy data width conversion without any
  additional logic

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Dual-Port RAM used as 1024x18 ROM
RAMB4_S4_S16
0 1 0
WEA
ENA
Clk_ROM
Data170
RSTA
DOA170
CLKA
ADDRA90
Addr90
DIA170
WEB
All inputs of PORT B and data inputs of PORT
A connected to 0
ENB
Outputs of PORT B left unconnected
RSTB
DOB150
CLKB
ADDRB70
DIB150
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Initializing Block RAMs
INIT_00 BIT_VECTOR X"014A0C0F09170A04076802A8
00260205002A01C5020A0917006A006800060040" INIT_01
BIT_VECTOR X"000000000000000008000A1907070A1
706070A020026014A0C0F03AA09170026" INIT_02
BIT_VECTOR X"0000000000000000000000000000000000
000000000000000000000000000000" INIT_03
BIT_VECTOR X"0000000000000000000000000000000000
000000000000000000000000000000"
INIT_0F
BIT_VECTOR X"0000000000000000000000000000000000
000000000000000000000000000000")
DATA
ADDRESS
Addresses are shown in red and data corresponding
to the same memory location is shown in black
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Contents of the Program Memory
16 bits stored
ADDR 00 01 02 03 04 . FD FE FF
0 0 4 0 0 0 0 6 0 0 6 8 0 0 6 A 0 9 1 7 . 0 0
0 0 0 0 0 0 0 0 0 0
256 memory locations
12 bits read
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Experiment 7
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Experiment 7 Part 1
RESET
Set Port Directions
Sum lt 0 Counter lt 0
Wait for a rising edge at Port C(0)
Wait for a rising edge at Port C(0)
Port B lt Sum(3 downto 0)
Sum lt Sum Port A Counter lt Counter 1
N
Wait for a rising edge at Port C(0)
If PORT(C(1)1) PortBltSum else PortB lt PortA
Counter 4?
Y
Port B lt Sum(7 downto 4)
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Experiment 7 Part 2
Implement PICREG Register File using
Distributed RAM present in all CLB slices
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CLB Slice Structure

• Each slice contains two sets of the following
• Four-input LUT
• Carry Control
• Storage element

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Distributed RAM

• CLB LUT configurable as Distributed RAM
• A LUT equals 16x1 RAM
• Implements Single and Dual-Ports
• Cascade LUTs to increase RAM size
• Synchronous write
• Synchronous/Asynchronous read
• Accompanying flip-flops used for synchronous read

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Experiment 7 Bonus

• Choosing maximum out of the entered
• four numbers
• 2. C program for an automated conversion of a
  PIC
• .hex file to the sequence of initialization
  strings
• for Xilinx Block RAMs INIT_00, INIT_01, etc.

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Questions?