The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the FPX

1
The FPX KCPSM ModuleAn Embedded, Reconfigurable
Active Processing Module for the FPX
Henry Fu Washington University Applied Research
Lab Supported by NSF ANI-0096052 and Xilinx
Corp. http//www.arl.wustl.edu/arl/projects/fpx/f
px_kcpsm/ hwf1_at_arl.wustl.edu
2
Motivation

• Hardware plugins are well suited for processing
  data with high throughput
• Software plugins are well suited for implementing
  complex control functions
• Need a hybrid plugins that can implement complex
  control functions with high data throughput

3
Introduction

• The FPX KCPSM module is a hardware plugin that
  executes software on an embedded soft-core
  processor
• It implements active networking functions on the
  FPX using both hardware and software
• It includes circuits to be reprogrammed over the
  network and to execute new programs between the
  processing of data packets

4
Overview

• The FPX KCPSM Module is composed of three parts
• The KCPSM, a 8-bit microprocessor developed by
  Xilinx Corp.
• The Protocol Wrappers, a circuit used to simplify
  the processing of ATM cells, AAL5 frames, IP
  packets, and UDP datagrams
• The Interface, a circuit used to interconnect the
  KCPSM and the Protocol Wrappers

5
The FPX KCPSM Module
KCPSM
INST
ADDR
PORT_ID
I/O
BUS
DATA
PROGRAM
UDP PACKETS
UDP PACKETS
ATM CELLS
ATM CELLS
MEMORY
MEMORY
ADDR
INST
ADDR
DATA
BUS
D_OUT_MOD
D_MOD_IN
D_MOD_IN
D_OUT_MOD
INTERFACE
SOC_MOD_IN
SOC_OUT_MOD
CONTROL
CONTROL
TCA_MOD_IN
TCA_OUT_MOD
SIGNALS
SIGNALS
PROTOCOL WRAPPERS
CLK
RESET_L
ENABLE_L
READY_L
6
Features

• Software can be loaded over the network through
  the use of UDP datagrams
• Up to four data packets and up to two programs
  can be stored in the module at a time
• The processing function can be changed
  dynamically, on a packet by packet basis

7
Background of the FPX

• The FPX (Field Programmable Port Extender)
• A reprogrammable logic device that provides a
  hardware platform to deploy network modules
• It is composed of two parts
• NID (Network Interface Device), a circuit that
  interconnects the WUGS (Washington University
  Gigabit Switch), the line cards, and the RAD
• RAD (Reprogrammable Application Device), a
  circuit that can be reprogrammed to hold
  user-defined network modules

8
Configuration of the FPX

• The FPX acts as an interface between the line
  cards and the WUGS

FPX
Line
Card
IPP
OPP
Field-
programmable
OC3/
IPP
OPP
Port
OC12/
Extender
OC48
Gigabit
Switch
Fabric
FPX
Line
IPP
OPP
Card
Field-
IPP
OPP
OC3/
programmable
OC12/
Port
OC48
Extender
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Major Components of the FPX
KCPSM
Loopback
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Background of the KCPSM

• The KCPSM (Constant (K) Coded Programmable State
  Machine)
• A 8-bit microcontroller
• Consumes only 35 CLBs in FPGA
• Provides 49 different instructions, 16 registers,
  256 directly and indirectly addressable ports,
  and a maskable interrupt
• Runs at a maximum frequency of 70 MHz
• Developed by Ken Chapman of Xilinx Corp.

11
Background of the KCPSM (More)

• The KCPSM
• Designed for Xilinx Virtex and Spart-II devices
• Provided in the form of an EDIF macro
• Included an assembler and debugger

12
Downloading the KCPSM Package

• The KCPSM Package from Xilinx Corp.
• Visit
• http//www.arl.wustl.edu/arl/projects/fpx/fpx_kcps
  m
• Left click on the KCPSM package
• Open the ZIP file
• Extract to h\xilinx
• Start Cygwin Bash Shell
• Engineering gt FPGA Tools gt Cygwin Bash Shell
• cd /cygdrive/h/xilinx/

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Contents of the KCPSM Package

• Access the KCPSM Package
• An assembler called KCPSMBLE
• ./KCPSMBLE debug.psm
• An debugger called PSMDEBUG
• ./PSMDEBUG debug.coe
• Documentations
• A modified KCPSM package that includes example
  programs will be included as part of the FPX
  KCPSM package during the exercise

14
Background of the Protocol Wrappers

• The Protocol Wrappers
• A circuit that streamline the networking
  functions to process ATM cells, AAL5 frames, IP
  packets, and UDP datagrams
• A layered design that consists different
  processing circuit in each layer
• Allows application to be implemented at a level
  where important details are exposed and
  irrelevant details are hidden

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Overview of the Protocol Wrappers

• The Protocol Wrappers is composed of four
  circuits
• Cell Processor processes raw ATM cells between
  network interfaces
• Frame Processor processes variable length AAL5
  frames
• IP Processor processes IP packets
• UDP Processor sends and receives UDP datagrams

16
Overview of the Protocol Wrappers (More)
Interfaces to Off-Chip Memories
Application-level Hardware Module
Data Output
Data Input
17
Downloading the Wrappers Package

• The Protocol Wrappers Package
• Visit
• http//www.arl.wustl.edu/arl/projects/fpx/fpx_kcps
  m
• Right click on the Wrappers Package
• Save it to h\
• Start Cygwin Bash Shell
• Engineering gt FPGA Tools gt Cygwin Bash Shell
• cd /cygdrive/h/
• gunzip wrappers.tar.gz
• tar xvf wrappers.tar

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Contents of the Protocol Wrappers Package

• Access the Protocol Wrappers Package
• Cell Processor
• cellwrapper.vhdl, the VHDL instantiation file
• cellproc_sim.vhd, the VHDL simulation file
• cellproc.edn, the EDIF Macro synthesis file
• Frame Processor
• framewrapper.vhdl, the VHDL instantiation file
• frameproc_sim.vhd, the VHDL simulation file
• frameproc.edn, the EDIF Macro synthesis file

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Contents of the Protocol Wrappers Package

• IP Processor
• ipwrapper.vhdl, the VHDL instantiation file
• ipproc_sim.vhd, the VHDL simulation file
• ipproc.edn, the EDIF Macro synthesis file
• UDP Processor
• udpwrapper.vhdl, the VHDL instantiation file
• udpproc_sim.vhd, the VHDL simulation file
• udpproc.edn, the EDIF Macro synthesis file
• COREGEN Components

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Overview of the Interface

• The Interface
• A circuit that interconnects the KCPSM and the
  Protocol Wrappers
• Switches the source and destination IP address
  and UDP port numbers, buffers the incoming UDP
  packets and stores them to the memory, resets the
  KCPSM, and writes the outgoing UDP packets back
  to the sender

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Overview of the Interface (More)

• The Interface is composed of seven control units
• UDP Packets Header Switch
• UDP Packets FIFO Control
• UDP Packets Type Check
• UDP Packets Store Control
• KCPSM Reset Control
• Unmodified Program Packets Echo Control
• Completed Data Packets Write Control

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Overview of the Interface (More)
KCPSM
Control
Control
Signals
Signals
ADDR
INST
ADDR
DATA
Program
Data
KCPSM
Memory
Memory
Reset Control
Completed
Data
Packet
Program
Data
UDP Packets
Data Packets
Packet
Packet
FIFO Control
Write Control
Control
UDP
Write
Buffered
Signals
Packet
UDP
Grant
Packet
UDP Packets
UDP Packets
FIFO
UDP
UDP
Header Switch
Store Control
Packet
Packet
Unmodified
Program
UDP
Control
Packet
Packet
Signals
UDP Packets
Program Pkts
Type Check
Echo Control
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Overview of the Interface (More)
KCPSM
Control
Control
Signals
Signals
ADDR
INST
ADDR
DATA
Program
Data
KCPSM
Memory
Memory
Reset Control
Completed
Data
Packet
Program
Data
UDP Packets
Data Packets
Packet
Packet
FIFO Control
Write Control
Control
UDP
Write
Buffered
Signals
Packet
UDP
Grant
Packet
UDP Packets
UDP Packets
FIFO
UDP
UDP
Header Switch
Store Control
Packet
Packet
Unmodified
Program
UDP
Control
Packet
Packet
Signals
UDP Packets
Program Pkts
Type Check
Echo Control
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UDP Packets Header Switch Control

• UDP Packets Header Switch Control
• Switches the source and destination IP address
  and UDP Port numbers of the UDP packets
• Allows the unmodified program packets and
  completed data packets to be echoed back to the
  sender

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UDP Packets FIFO Control

• UDP Packets FIFO Control
• Buffers incoming UDP packets
• Delays the arrival of the UDP packets to the UDP
  Packets Store Control so that it can wait for the
  result from the UDP Packet Type Check in order to
  determine whether to store the UDP packets into
  the program memory or into the data memory

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UDP Packets Type Check

• UDP Packets Type Check
• Determines if the incoming UDP packets is a
  program packet or a data packet
• Inspects the first word of the UDP payload
• 0x00000000 indicates a program packet
• 0x00000001 indicates a data packet

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UDP Packets Store Control

• UDP Packets Store Control
• If the incoming packet is a program packet
• Stores the UDP payload, except the first word,
  into the program memory
• If the incoming packet is a data packet
• Stores the whole packets, including the ATM, AAL5
  Frame, IP and UDP headers, the UDP payload, and
  the ATM trailers into the data memory
• Increments the bank counters so that the next UDP
  packet will store into the next available bank of
  memory

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KCPSM Reset Control

• KCPSM Reset Control
• Resets the KCPSM by asserting the Interrupt input
  of the KCPSM for two clock cycles
• If there is no new program loaded
• Resets the KCPSM so that it processes the next
  available data packets using the current program
• If there is a new program loaded
• Resets the KCPSM and increments the program
  counter so that it processes the next available
  data packets using the new program

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Unmodified Program Packets Echo Control

• Unmodified Program Packets Echo Control
• Echoes the incoming program packets back to the
  sender
• Passes any non-UDP packets through the module

30
Completed Data Packets Write Control

• Completed Data Packets Write Control
• Writes the completed data packets back to the
  sender only if
• they have been processed by the KCPSM
• there is no new incoming data packet by
  inspecting the WR_GRANT signal from the UDP
  Packets Store Control

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The FPX KCPSM Module Demo

• Network Data Compression using RLE (Run-Length
  Encoding) Algorithm
• Compression example
• AAAABBBC compresses to A4B3C
• Decompression example
• A4B3C decompresses to AAAABBBC
• Allowed input characters range from A to Z,
  a to z

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The FPX KCPSM Module Demo (More)

• Log on to fpx.arl.wustl.edu / fpx2.arl.wustl.edu
  using SSH (Secure Shell)
• fpx / fpx2 is connected to the line cards / fpx
  boards / WUGS
• fpx / fpx2 directs network traffic to the line
  cards / fpx boards / WUGS
• IP over ATM is configured on fpx / fpx2 to send
  UDP packets on VCI / VPI 96

33
The FPX KCPSM Module Demo (More)

• A C program called UDPTEST is executed on the fpx
  / fpx2 and is used to send program packets to the
  FPX KCPSM module
• Download URL
• http//www.arl.wustl.edu/arl/projects/fpx/fpx_kcps
  m/
• Usage
• ./UDPTEST RLEEN.TBP (Encoder)
• ./UDPTEST RLEDE.TBP (Decoder)
• The ltFILENAME.TBPgt file contains the raw machine
  code of the KCPSM program

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Program Packet Processing
Independent
KCPSM
Process
ADDR
INST
ALTERNATE
CURRENT
BANK
BANK
PROGRAM
MEMORY
Proceed as long as
Proceed as long as
there is new incoming
there is new incoming
program packet
INST
ADDR
program packet
INTERFACE
Program
Packet
Packet
Program
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The FPX KCPSM Module Demo (More)

• A C program called UDPSTR is executed on the fpx
  / fpx2 and is used to send data packets
  containing character strings to the FPX KCPSM
  module
• Download URL
• http//www.arl.wustl.edu/arl/projects/fpx/fpx_kcps
  m/
• Usage
• ./UDPSTR -h hostname -p destination port
• Enter the character strings in the input prompt

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Data Packet Processing
Proceed as long as
KCPSM
there is data packet
ADDR
I/O
BUS
ALT
ALT
ALT
CUR
BANK
BANK
BANK
BANK
DA
MEM
TA
ORY
Proceed as long as
Proceed as long as
there is new
there is completed data packet
ADDR
DATA
ADDR
DATA
incoming data packet
and no new incoming data packet
BUS
BUS
INTERFACE
Data
Packet
Data
Packet
37
The FPX KCPSM Module (Demo)

• Screenshot of the compression example

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The FPX KCPSM Module Demo (More)

• Screenshot of the decompression example

39
Synthesis Results

• The FPX KCPSM Module is synthesized to a Xilinx
  XCV1000E-7-FG680
• Maximum Frequency 70 MHz
• Chip Utilization 35 (4305 / 12288 slices)
• External Input Buffers 69 uses
• External Output Buffers 105 uses
• Total LUTS 3807 uses

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Synthesis Results (More)

• The Xinlinx backend synthesis script
• ngdbuild -p xcv1000e-7-fg680 -uc design.ucf
• map -p xcv1000e-7-fg680 -o top.ncd design.ngd
  design.pcf
• par -w -ol 2 top.ncd design.ncd design.pcf
• trce design.ncd design.pcf -e 3 -o design.twr
  -xml design_trce.xml
• bitgen design.ncd -b -l -w -f bitgen.ut

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Conclusion

• The FPX KCPSM Module
• Demonstrates how to embed a softcore processor
  and how to use the Protocol Wrappers in an FPX
  module
• Combines software flexibility and hardware
  performance into a hybrid module
• Targets to work with the KCPSM, WUGS, FPX
  research environment, but can easily be changed
  to work with any FPGA-based system