Low Power

1
Low Power High Speed MCML Circuits (II)
Shahnam Khabiri 95.575 March, 2002
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Outline

• Introduction
• CSL and MCML operation
• CMOS, MCML, CML, ECL comparison
• DyCML
• Feedback MCML
• Adaptive pipeline system for MCML
• Conclusion
• References

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Introduction

• VLSI development goals

• - Large integration density
• High speed operation
• Low power dissipation
• Low cost

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Introduction

• Why not CMOS

• Why CMOS

• - High packing densities
• High noise margin
• Simplicity
• No static power dissipation
• Yield
• Low cost,

• Switching noise in mixed mode ASICs
• f ? ? P ?
• Vdd ? ? P ?, but Delay ? ,

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Current Steering Logic (CSL)

• Advantage

• Reduced power supply current noise

• Disadvantage

• Additional output branch for each fanout
• Static power dissipation
• Frequency proportional dynamic power
  dissipation

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MCML Operation

• Rise time depends on RL (RFP voltage)
• Fall time depends on I (RFN voltage)
• NMOS current source has longer L to provide high
  ro
• Less sensitivity to noise margin and gain,
  therefore
• gain could be set to 1.4
• and Vswing set to 300mv

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MCML Logic Gates
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CMOS, MCML, CML, ECL
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CMOS, MCML, CML, ECL
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Simulated results for an MCML F.A.

• MCML Full Adder in 0.5um
• Vdd 1.2 v
• delay 200ps
• CMOS
• Vdd 3.3 v, delay 600ps
• Vdd 1.5 v, delay 2ns

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Experimental results for an MCML F.F

• 0.5 um cmos, f 1.8 GHz
• Delay between clock edge and output 160ps

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DyCML

• Vswing.CL WC1.LC1.Cox.(Vdd-Vswing)
• C1 size

• Advantage

• Dynamic current source
• No static power dissipation
• More stability in compare with other dynamic
  circuits
• Supply voltage is as low as VtnVtp

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DyCML

• Cascading

1- Clock Delay mechanism (CD) less stability 2-
Self Timing scheme (ST) higher delay and power
consumption
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Simulation results for DyCML

• Using 0.6 um CMOS
• Vdd 3.3 v, f 100MHz
• DyCML more suitable for complex gates
• ST is slower than CD and consumes more power

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Feedback MCML

• Effect of Vth fluctuation

• Vth fluctuation is due to
• Fluctuation of gate oxide thickness
• Fluctuation of gate length
• Random placement of the channel dopant
• ?VB G(0).?Vth
• G(0)? ? ?VB?

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Feedback MCML

• If GC(fmax) GF(fmax)
• ? GF(0) lt GC(0) ?
• ?VB is smaller ?
• More tolerance for ?Vth _at_ several GHz
• - LMF1 and LMF2 are larger than minimum

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Feedback MCML 12 Demux and simulation results

• Feedback MCML tolerates two times more Vth
  fluctuation in compare with conventional MCML
• Experimental results show 10 Gb/s Mux, Demux 18
  in 0.18um use ¼ power of GaAs or Si bipolar and
  faster than CMOS.

• Feedback MCML Latch implementation

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MCML Optimization in Mixed Signal Applications

• Voltage Swing Control (VSC)

• VSC allows fixed voltage swing across variety of
  currents and easy trade off speed for power
• Drawbacks
• Power and area overhead
• different gates wont track Vlow exactly so
  hard to share VSC

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Adaptive pipeline system for MCML

• Current Source Controller

• RFN and consequently I will be set based on
  critical path delay requirements
• Circuit timing insensitive to process,
  temperature and voltage variation.
• Design for nominal delay and not the worst case
  delay

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Full Adder in MCML

• We can use Current scaling to increase Carry
  speed
• For small number of bits lt16 bits CLA is not a
  great help

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Experimental Results

• Using 0.25 CMOS process for a 12 bits CORDIC
  Full Adder
• Power results of MCML are up to 1.5 times less
  than CMOS CORDICs with similar propagation

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Conclusion

• MCML advantages

• High speed
• Tcmos gt Tmcml gt Tcml gt Tecl
• NMOS devices, Low voltage swing, All ON
  Transistors
• Low power consumption
• _at_500MHz with applicable Vdds
• Pcmos gt Pecl gt Pcml gt Pmcml
• Flexible to construct any logic circuit
• High speed compact circuits are feasible
• P is constant with increasing f (good for high
  speed applications)
• Fixed power supply current (good for mixed
  signal ASICs)
• Vdd? ? P? , No effect on Delay

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Conclusion

• MCML advantages

• Small Vswing reduces cross talk
• Common noise rejection capability
• MOS related advantages
• good yield, small area, low cost, low supply
  voltage
• No theoretical minimum for E.D
• For a linear chain of N identical MCML gates
• E.D N3.C2.Vdd.?V2/I
• I? ? E.D?
• Flexibility in design optimization
• Vswing, I, Vdd, Transistor sizes

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Conclusion

• MCML disadvantages

• ?VT deviation impact on functionality and delay
• Static power
• Not suitable for power down mode systems
• Large load resistors need large area
• Matching of rise and fall delays
• Shallow depth logic is a limit for MCML

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References

• Yamashina, Yamada,An MOS Current Mode Logic
  Circuit for Low Power GHz Processors, NEC Res
  Dev, 1995.

• J.Rabaey, J.M.Musicer,MOS current mode logic for
  low power, low noise CORDIC computation in mixed
  signal environment, 2000.

• A.Tanabe,0.18 u CMOS 10 Gb/s Multiplexer/Demultip
  lexer Ics using current mode logic with tolerance
  to Threshold Voltage fluctuation,IEEE J. Solid
  State Circuits, Vol36, No 6, June 2001.

• M.W.Allam, M.I.Elmasry,Dynamic current mode
  logic a new low power high performance logic
  style,IEEE J. Solid State Circuits, Vol36, No 3,
  March 2001.

• D.J.Allostot,Current mode logic techniques for
  CMOS mixed-mode ASICs,IEEE Custom Integrated
  Circuits Conf., 1991.