EC64 Digital System Design using VHDL Question paper solution JulyAug 2005

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EC64 Digital System Design using VHDLQuestion
paper solutionJuly/Aug 2005 UMA B.V.RVCE
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4(a) Implement traffic light controller using
74163 counter with added logic. Use ROM to
generate the outputs. State graph of Traffic
controller
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Each street A and B has traffic sensors, which
detect the presence of vehicles approaching or
stopped at the intersection. Sa 1 means a
vehicle is approaching on A street, and Sb1
means a vehicle is approaching on B street.
A street is a main street and has a green
light until the car approaches on B. Then the
light changes and B has a green light. At the
end of 50 seconds, the light changes back unless
there is a car on B street and none on A, in
which case the B cycle is extended to another
10 more seconds.
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When A is green, it remains green at least 60
seconds, and then the lights change only when the
car approaches on B. The external connections
to the controller are three outputs (Ga, Ya, Ra)
drives the green, yellow and red lights on the
A street. The other three (Gb, Yb, Rb) drives
the green, yellow and red lights on the B
street.
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ROM table for traffic controller

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Added logic (1) Clear when Q3Q21 i.e. S12
Therefore clrn (Q3Q2) (2) Count except in S5,
Sb'1 and in S11, Sa'Sb 1 So PT
(Q2Q1'Q0Sb' Q3Q2'Q1Q0Sa'Sb)
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Working Counter outputs are used to address the
ROM. ROM contents are outputs of each states
from S0 to S12. The first address contains 6 bit
information for GaYaRa GbYbRb of state S0 The
second address contains 6 bit information for
GaYaRa GbYbRb of state S1 and so on. When
counter counts from 0 to 11, address of the ROM
changes hence the corresponding street lights
turn on and off by the contents of the
corresponding memory location. Note The state
change is achieved by counter.
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5(b) Realize the control circuit of 4 bit serial
multiplier using a PLA and D flipflops.
Digital circuits required Two counters to count
from 0 to 3. one counter counts number of bits to
be added for every bit multiplication, other
counter to count number of bits to be
multiplied. One Full adder, three D flipflops
and one PLA.
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Circuit diagram for serial Adder for multiplier
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• PLA realization

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Signals K1 terminal count output of 0 to 3
counter for 4 bit addition K2
terminal count output of 0 to 3 counter for 4 bit
multiplication. M multiplier bit
St start pulse Sa right
shift signal for A register Sb
right shift signal for B register
Sc right shift signal for C register Note Clock
for B register is ¼ times the clock of A and C
register so that every 4 th clock pulse partial
product is shifted to B register and multiplier
bit shifts right one bit right.
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5(c) Write a VHDL code for 2 input NOR GATE with
-rise/fall time modeling using generic
statement. Entity NOR2 is generic(trise, tfall
time load integer) Port(a,b in bit cout
bit) End NOR2 Architecture behave ofNOR2 is
Signal nor_value bit
Begin nor_value lt a nor
bcltnor_value after (trise3 ns load) when
nor_value 1 else nor_value after (Tfall2 ns
load)end behave
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7(a) The PLA realization of a dice game is as
shown in fig. Write a VHDL code for the
same.
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library ieee use ieee.std_logic_1164.all --
ieee standard logic package library mvllib --
includes plamtrx type and use mvllib.mvl_pack.all
-- plaout function entity pladice is port ( Rb,
Res, D711, D7, D2312, Eq , clk in
std_logic win, lose, roll, Sp out
std_logic) end pladice architecture pla of
pladice is signal q, qplus std_logic_vector ( 1
to 3) "000"
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constant fsm_pla plamtrx (0 to 17 , 15 downto
0) ("0000-----0000000", 0001-----0010000",
.) begin process (Rb, Res, D711, D7,
D2312, Eq , clk q,) variable plavalue
std_logic_vector(6 downto 0) variable
xstdlogic begin x Rb Res D711 D7 D2312
Eq plavalue plaout(fsm_pla,q x) --
read pla output qplus lt plavalue (6 downto
4) win lt plavalue(3) lose lt plavalue(2) roll
lt plavalue(1) Sp lt plavalue(0) end process
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process(clk) begin if clk'1' then q lt qplus
end if -- update state register end
process end pla
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8 (c).Write a VHDL model for N bit bidirectional
shift register using a generic statement. Define
a component that represents one bit of the shift
register. The component port should be Port(L,R,
CLR, CLK, Pin, Lin,Rin in bit q out bit) such
that LR00 should do nothing, LR01 shift right,
LR10 shift left and LR11 parallel load. entity
shifter is generic(N integer8)
port(L.,R,CLR,CLK, SLin, SRin, in bit
Pin in bit_vector(N downto 1)
Qout out bit_vector(N downto 1) end
shifter Architecture behavioral of shifter
is component bitshifter is port( L,R,
CLR, CLK, Pin,Rin,Lin in bit Q
out bit) end component
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signal reg bit_vector(N downto 1) begin
Qoutltreg reg_1 bitshifter
port map (L,R,CLR,CLK,Pin(1),reg(2),SRin,r
eg(1)) Gen for I in 2 to N-1 generate
begin Reg_ibitshifter
port map(L,R,CLR,CLK,Pin(I),reg(I1),reg(I-1),reg(
I)) End generate gen Reg_Nbitshifter
port map(L,R,CLR,CLK,Pin(N),SL(in),reg
(N-1),reg(N)) End behavioral ------------------
--------------------------------------------------
-----------------------------
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Entity bitshifter is Port(L,R,CLR,CLK,Pin,Lin,Rin,
in bit Q out bit) end
bitshifter Architecture shift of bitshifter
is Begin Process(CLK,CLR) Begin if CLR1 then
Qlt0 Elsif CLK1 and CLK event then If
(L0 and R1) then QltRin
--right shift Elsif (L1 and R0) then
QltLin --left shift Elsif (L1 and
R1) then QltPin --parallel load End
if End if End process End shift