Logic Synthesis 5 FSM and Retiming

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Logic Synthesis 5FSM and Retiming

• Ahmed Hemani
• Sources
• Synopsys Documentation

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Multi Cycle Paths
Timing path that is not expected to propagate a
signal in one cycle
To undo a set_multicycle_path command use
reset_path or reset_design.
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False Paths
You can exclude false paths from an Static Timing
Analysis run. False paths are considered
unconstrained.
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Pipelining a fully manual approach
Increases the throughput of designs to meet high
timing constraints.
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Re-timing a semi-automatic approach
Increases the throughput of designs to meet high
timing constraints.
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Re-timing - Limitations
Only works on mapped/compiled designs
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Re-timing registered outputs
How to get the output registers right?
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Finite State Machines
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Synthesis of Finite State Machines
Idea - Make Synopsys aware of that the logic
represents an FSM
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Synthesis flow of FSMs in Synopsys
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Synthesis Flow of FSMs in Synopsys

• Extraction of the state-vector in a design where
  the state-vector is not the only sequential
  elements
• dcgt analyze -f vhdl state_vector.vhdl
• dcgt elaborate fsm -arch fsm_behave
• dcgt group -fsm -design_name extracted_fsm
• dcgt current_design extracted_fsm
• dcgt replace_synthetic
• dcgt extract
• dcgt report -fsm
• Extraction of the state-vector in a design where
  the state-vector attribute is not set in the HDL
• Existing Registers
• U1FLIP_FLOP port map (NEXT_STATE0, CLK,
  STATE0)
• U2FLIP_FLOP port map (NEXT_STATE1, CLK,
  STATE1)
• How to give the register the state attributes
• set_fsm_state_vector U1, U2
• set_fsm_encoding "S0200", "S1201",
  "S2210", "S3211"
• Use the script above for the rest

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Synthesis flow of FSMs in Synopsys