Foundations of Reachability Analysis

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Foundations of Reachability Analysis
EECS 290A Sequential Logic Synthesis and
Verification Lecture 1
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Overview

• Sequential systems are systems with memory
  elements
• Behavior can be characterized in terms of states
  and transitions
• States can be initial, reachable, unreachable,
  etc
• Reachability analysis deals with determining the
  set of reachable states
• The reachable state information is useful in
• Logic synthesis (external dont-cares)
• Formal verification (proving a property for
  reachable states)
• Reachability analysis of large systems is a
  complex task attracting significant research
  efforts

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Descriptions of Sequential Systems

• State level

• Structural level

State transition graph (STG), automaton, FSM
Circuit, logic network

• States is a higher level description, compared to
  structure
• Going from structure to states is STG extraction
• Going from states to structure is implementation
  (encoding and logic synthesis)

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Types of States

• A state characterizes the behavior of a
  sequential system, given a fixed set of values of
  the memory elements
• Initial state A state, in which the system
  begins its functioning.
• Reachable state A state that can be reached from
  the initial one though a finite sequence of
  transitions under allowed inputs.
• Unreachable state A state that cannot be reached
  from the initial under any sequence of inputs.

Reachable states
Unreachable states
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State Level Descriptions
Automaton
Non-Deterministic FSM
Deterministic FSM
Pseudo-Non-Deterministic FSM
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Structural Level Descriptions
Latch outputs (LO)
Primary outputs (POs)
Latches
Latch inputs (LI)
Latches
PO
LI
Internal nodes
Logic
LO
PI
Primary inputs (PIs)
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Fanin/Fanout of a Node

• Node has only one output.
• Node can have any number of inputs (fanins) and
  can be an input to any number of nodes (fanouts)

FO1
FO2
FO3
Fanouts
N
Node
FI2
FI3
FI1
Fanins
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Transitive Fanin/Fanout of a Node
Transitive fanout (TFO)
Node
Transitive fanin (TFI)
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Reachability Onion Rings
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Computation of Reachable States

• Input Sequential system represented by a
  transition relation and an initial state (a set
  of initial states)
• Computation Image computation, set operations on
  sets of states
• Output A set of reachable states

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Relation

• Definition. Relation is a subset of the product
  of two sets, R A x B. If (a, b) is an element
  of R then we write a R b, meaning a is related to
  b by R.

x1 x2 x3 y1 y2
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 0
1 0 1 0 1
1 1 0 1 1
1 1 1 1 1
x1
y1
x2
y2
x3
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Characteristic Function

• Relation R A x B can be represented by a
  characteristic function a Boolean function
  FR(a,b), a ?A, b ?B taking value 1 for those a
  and b that belong to relation R.

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Example (continued)
x1 x2 x3 y1 y2 F
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 0 1 1
1 0 0 0 0 1
1 0 1 0 1 1
1 1 0 1 1 1
1 1 1 1 1 1
0
x1
x2
x3
y1
y2
0
1
other
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Transition Relation

• Definition. An FSM is ltI, O, S, ?, ?, S0 gt.
• Definition. A transition relation of an FSM is a
  relation R I x S x S that is true for a pair of
  states s1 and s2, iff there is a transition
  between them under some input.

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Transition Relation of an FSM
I CS cs1 cs2 NS ns1 ns2
0 A 00 B 10
0,1 A 00 A 00
0 B 10 B 10
1 B 10 A 00
0 C 01 B 10
1 C 01 A 00
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Example (continued)
i
cs1
ns1
cs2
ns2
1
0
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Reachability Pseudo-Code

• Reachability( Transition Relation TR, Initial
  State I )
• ReachedStates I
• iterate the following computation
• ReachedStatesNew Image( TR, ReachedStates )
• if (ReachedStatesNew is contained in
  ReachedStates )
• stop
• ReachedStates ReachedStates ReachedStatesNew

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Image Computation

• Given a mapping of one Boolean space (input
  space) into another Boolean space (output space)
• For a set of minterms (care set) in the input
  space
• The image is the set of related minterms from the
  output space
• For a set of minterms in the output space
• The pre-image is the set of related minterms in
  the input space

Output space
Input space
Image
Care set
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Example
Input space
abc
000
y
x
Output space
Care set
001
xy
010
00
Image
011
01
a
b
c
100
10
101
11
110
111
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Image Computation

• Implements formula Image(Y) ?x R(X,Y) C(X)
• Implicit methods by far outperform explicit ones
• Successfully computing images with more than
  2100 minterms in the input/output spaces
• Operations and ? are basic Boolean
  manipulations are implemented using BDDs
• To avoid large intermediate results (during and
  after the product computation), operation
  AND-EXIST is used, which performs product and
  quantification in one pass over the BDD

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Image Computation Techniques

• When the relation is a monolithic one
  (represented as a single object), these
  techniques do not work
• Sometimes the relation can be decomposed using
  disjoint-support decomposition, etc.
• Some techniques work for a partitioned
  representation
• This representation is natural when the system is
  represented on the structural level
• In this case, the transition relation is given in
  the form of the set of partitions
• T(x,cs,ns) ?i Ti(x,cs,nsi)

Latches
ns
cs
x
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Input Splitting
Input space

• Select an input variable
• Cofactor partition w.r.t. this variable
• Compute the images for the cofactors
• Union the resulting images

abc
000
Output space
Care set
001
xy
010
00
Image
011
01
x a b y bc
100
10
a1
a0
101
11
x b y bc
x 1 y bc
110
111
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Output Splitting

• Constrain each function Yi(x) w.r.t the care set
  C(x)
• Recursively compute the image as follows
• Select an output variable yi
• Constrain each remaining function using the
  function yiYi(x)
• Use the direct polarity
• Use the complemented polarity
• Find the images of the two resulting sets of
  functions, Im1(y) and Im2(y)
• Combine the images using the ITE operator and the
  variable yi.
• Im(y) ITE(yi, Im1(y), Im2(y))
• Trivial cases
• When function Yj(x) is constant 0 (1), the image
  is yj (yj)
• When there is only one non-constant function
  left, the image is constant 1 (it does not depend
  on the y variables)
• When functions in the set Y can be split into two
  parts with disjoint support, the image is the
  product of the two images
• When only two functions are left and, for
  example, Yj1(x) Yj2(x), then, the image is yj1
  ? yj2

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Input vs. Output Splitting

• These two methods are symmetric w.r.t.
  inputs/outputs
• Their efficiency depends on the cardinality of
  I/O spaces
• In some problems, output splitting is more
  efficient because the output space is smaller
  than the input space
• As a result, the (potentially exponential) tree
  depth is bounded by a smaller number

Variable 1
Variable 2
Variable 3
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Quantification Scheduling

• Existential quantification and product commute if
  a variable to be quantified belongs to only one
  component in the product
• ?x F(x,y) G(x,y) ? ?x F(x,y) ?x G(x,y)
• ?x F(y) G(x,y) F(y) ?x G(x,y)
• Scheduling is performed by ordering the
  partitions, so that the variables are quantified
  as early as possible
• Image(Y) ?x,i A(x) T1(x,i,y) T2(x,i,y)
  Tk(x,i,y)
• ?xk,ik Tk(x,i,y)
• ?xk-1,ik-1 Tk(x,i,y)
• ?x1,i1 T1(x,i,y) ?x0,i0 A(x)
  

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Project Overview
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Project 1 Sequential optimization without state
space exploration

• The previous work 1 proposes a way to perform
  sequential optimization using recursive learning
  across latch boundaries. The goal of this project
  is to investigate possible extensions of this
  work, trying to get deeper understanding of the
  relationship of the algorithm with other
  sequential optimization techniques. Another goal
  is to develop an efficient implementation of this
  method in MVSIS.
• 1 A. Mehrotra, S. Qadeer, V. Singhal, R. K
  Brayton, A. L. Sangiovanni-Vincentelli, A. Aziz.
  Sequential optimization without state space
  exploration. Proc. ICCAD 97, pp. 208-215.

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Project 1 Sequential optimization without state
space exploration
Scope of recursive learning
Latches
PO
LI
Logic
LO
PI
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Project 2 Retiming of AND-INV graphs with latches

• Retiming moves latches around
• Retiming with unit-delay combinational blocks
  leads to the reduction of algorithm complexity
  1
• The project will explore the impact of the above
  fact when retiming is applied to the AIG 2
• 1 M. C. Papaefthymiou, Understanding retiming
  through maximum average-delay cycles. Math.
  Systems Theory, 27, 1994, pp. 65-84.
• 2 A. Mishchenko, S. Chatterjee, R. Jiang, R.
  Brayton. FRAIGs A Unifying Representation for
  Logic Synthesis and Verification. Submitted to
  DAC 05.

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Project 3 Performing retiming together with
technology mapping

• A study 1 has shown that the quality of results
  achieved by iterating retiming and technology
  mapping for FPGAs can be improved by integrating
  these transformations into one.
• This project will develop a similar technique for
  ASIC mapping 2 and study its impact on the
  mapping quality.
• 1 J. Cong and C. Wu, Optimal FPGA Mapping and
  Retiming with Efficient Initial State
  Computation, IEEE TCAD, vol. 18(11), pp 1595
  -1607, Nov. 1999.
• 2 A. Mishchenko, S. Chatterjee, R. Brayton, X.
  Wang, T. Kam. Technology Mapping with Boolean
  Matching, Supergates and Choices. Submitted to
  DAC

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Project 4 Sequential ATPG using simulation and
SAT

• Compare the efficiency of ATPG using
• Random simulation
• Bounded equivalence checking
• Unbounded equivalence checking
• The result of this experiment will help answer
  the following questions
• How many faults can be detected using the above
  techniques
• Whether bounded equivalence checking is a good
  method to generate tests for stuck-at faults in
  sequential circuits.

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Project 5 Implementation of windowing for
sequential optimization

• This project will focus on studying the available
  windowing schemes 1 for combinational networks
  and extending them to work for networks with
  latches. Several applications will be implemented
  and tested to show the impact of windowing on the
  runtime/quality trade-off. The applications may
  include reachability analysis, reencoding using
  the set of unreachable states, computation of
  combinational dont-cares due to unreachable and
  equivalence states using methods similar to 1.
• A. Mishchenko, R. Brayton. SAT-based complete
  dont-care computation for network optimization.
  Proc. IWLS 04.

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Project 6 PTL synthesis for testability

• (Mentor Rolf Drechsler, University of Bremen,
  Germany)
• One of the most important steps during circuit
  design is the testability of the netlist.
  Multiplexor circuits derived from BDDs have been
  studied intensively under various fault models.
  Recently, a new technique has been presented that
  guarantees full testability of a circuit derived
  from a BDD description under the stuck-at fault
  model and the robust path-delay fault model. The
  size of the circuit is directly proportional to
  the given BDD size.
• The goal of this project is to generalize the
  techniques 1 to work for sequential circuits,
  i.e. circuits that are not full-scan. The problem
  can be studied from a theoretical point of view
  or by an experimental study in the MVSIS
  environment.
• 1 R. Drechsler, J. Shi, G. Fey. Synthesis of
  Fully Testable Circuits from BDDs. IEEE Trans.
  CAD, Vol. 23(3), March 2004, pp. 440-443.

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Project 7 Verifying sequential circuits after
phase assignment

• (Mentor Geert Janssen, IBM T. J. Watson Research
  Center, Yorktown Heights)
• Two sequential netlists are available, one of
  them derived from the other by a phase assignment
  of the latches. The inverters are collapsed and
  the logic functions are restructured. The
  correspondence of latches in the two netlists is
  known. The problem is to check if the two designs
  are indeed equivalent under some phase
  assignment. A general-case sequential equivalence
  checking method can be used, but the question is
  if there exists a more efficient method
  applicable to the special type of the netlist
  after phase assignment.

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Project 8 Implementation of SAT-based sequential
equivalence checking

• Recent advances of SAT-solvers bring SAT
  formulation to one of the main streams in formal
  verification. However, most of the prior work on
  this subject aimed at general model checking.
  Since sequential equivalence checking is a very
  specific and practically important problem in
  design verification, presumably specialized
  algorithms (e.g. exploiting similarities of
  circuit structures) may further improve
  verification performance. This project studies
  the most recent development of SAT-based model
  checking, and applies it to the sequential
  equivalence checking problem. Students working on
  this project will get familiar with the
  verification area, and gain programming
  experience with an advanced SAT-solver.
• 1 K.L. McMillan. Interpolation and SAT-based
  model checking, Proc. CAV'03, LNCS 2725, 2003,
  pp. 1-13.

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Project 9 Resubstitution in sequential circuits

• This project will explore extensions of the
  notion of resubstitution for sequential circuits.
  The idea of one such extension comes from the
  following observation. If we consider two
  uninitialized consecutive time-frames of a
  sequential circuits as one combinational circuit,
  some nodes in the first frame can be
  resubstituted into the second frame. Going back
  to the original circuit, this transformation can
  be interpreted as adding a new latch to the
  circuit and reexpressing the logic function of a
  node in terms of the new latch. This reexpression
  may lead to simplification of the nodes local
  function, or to dropping fanins of the node,
  which may result in making redundant some latches
  of the original circuit.
• The goal of this project is to develop a theory
  supporting resubstitution in sequential circuits
  and implement an experimental command in the
  MVSIS environment, which will be applicable to
  large sequential circuits.

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Project 9 Resubstitution in sequential circuits
Latches
PO
LI
PO
LI
Logic
LO
PI
LO
PI
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Project 10 Using sequential flexibility to
synthesize redundant circuits for improved
reliability

• Study the last year project by Ruth Wang
• Generalize the problem statement to allow for
  different types of failures and additional
  feedback
• Develop a methodology to synthesize redundant
  circuits with improved reliability
• Implement the synthesis method and experiment on
  benchmarks