Lucas-Lehmer Primality Tester Presentation 2: Architecture Proposal February 1, 2006

1
Lucas-Lehmer Primality TesterPresentation 2
Architecture ProposalFebruary 1, 2006

• Team W-4
• Nathan Stohs W4-1
• Brian Johnson W4-2
• Joe Hurley W4-3
• Marques Johnson W4-4
• Design Manager
• Prateek Goenka

Overall Objective The Testing of Prime numbers
2
Status

• Finished
• Project Chosen
• C simulations
• Behavioral Verilog
• Structural Verilog
• Floor Plan
• In Progress
• Optimization of Structural Code
• To Do
• Schematic Design
• Layout
• Simulations

3
Design Decisions

• Current Implementation
• Ripple Carry Adder
• Serial Mod Multiplier
• Barrel Shifter
• Future
• Carry End Around Adder
• Use Sequential Logic

4
Adder Options

• Parallel-prefix Adders
• Serial-Prefix, which is the smallest but slowest
• Sklansky parallel-prefix, which is the fastest
  but lager
• End-around Carry-Adders
• Some take 2 propagations in series, which is slow
• Faster ones require two adders and a multiplexer,
  which is big

5
Modulo Multiply (2n-1)

• Has to do with partial products
• The algorithm calls for a Mod every time that
  there is a chance
• Example Mod 127
• 23
• X 56
• 18
• 120
• 150
• 1000

Leave
Leave
Mod
Mod
6
Structural Verilog Code

• module mod_mult(out, x, y, mod, p)
• input 150 x, y, mod, p
• output 150 out
• wire 150 pp00, pp01, pp02, pp03, pp04,
  pp05, pp06, pp07, pp08,
• pp09, pp10, pp11, pp12, pp13, pp14, pp15
• wire 150 ma0, ma1, ma2, ma3, ma4, ma5, ma6,
  ma7,
• ma8, ma9, ma10, ma11, ma12, ma13, ma14, maX
• partial_product ppg00(pp00, x, y, 4'b0000,
  mod, p)
• partial_product ppg01(pp01, x, y, 4'b0001,
  mod, p)
• partial_product ppg02(pp02, x, y, 4'b0010,
  mod, p)
• partial_product ppg03(pp03, x, y, 4'b0011,
  mod, p)
• partial_product ppg04(pp04, x, y, 4'b0100,
  mod, p)
• partial_product ppg05(pp05, x, y, 4'b0101,
  mod, p)
• partial_product ppg06(pp06, x, y, 4'b0110,
  mod, p)
• partial_product ppg07(pp07, x, y, 4'b0111,
  mod, p)
• partial_product ppg08(pp08, x, y, 4'b1000,
  mod, p)

mod_add CMA09(ma8, ma7, pp09, mod) mod_add
CMA10(ma9, ma8, pp10, mod) mod_add CMA11(ma10,
ma9, pp11, mod) mod_add CMA12(ma11, ma10,
pp12, mod) mod_add CMA13(ma12, ma11, pp13,
mod) mod_add CMA14(ma13, ma12, pp14, mod)
mod_add CMA15(ma14 , ma12, pp15, mod) sub_16
lastadd(.out(out), .cout(nowhere), .xin(ma14),
.yin(16'b10)) //assign out
(pp00pp01pp02pp03pp04pp05pp06pp07 // pp08
pp09pp10pp11pp12pp13pp14pp15-2)
mod endmodule
7
Simulation Results

• Fully simulates Mersenne Primes up to 30 Using
  the algorithm below
• Numbers above 230 make the code overflow because
  of the squaring in the algorithm
• 2P-1 is prime if and only if Sp-2 is zero in this
  sequence
• S0 4, SN (SN-12 - 2) mod (2P-1)

So for 27-1
S0 4 S1 (4 4 - 2) mod 127 14 S2 (14
14 - 2) mod 127 67 S3 (67 67 - 2) mod 127
42 S4 (42 42 - 2) mod 127 111 S5 (111
111 - 2) mod 127 0
Result says it is prime
8
Behavioral Simulation
S0 4 S1 (4 4 - 2) mod 127 14 S2 (14
14 - 2) mod 127 67 S3 (67 67 - 2) mod 127
42 S4 (42 42 - 2) mod 127 111 S5 (111
111 - 2) mod 127 0
9
Structural Simulation
10
Block Diagram for Prime Numbers
16
RegP
Mod Calc (1ltltp)-1
Reg2P-1
P
16
16
Counter 0P-2
Mod Serial Multiplier
16
16
16
16
Reg 4
Reg -2
16
Comparator Counter P-2
Check 0
1
16
Out
11
Mod Serial Multiplier Block Diagram
16
multiplicand
multiplier
Zero?
16
16
p
2p-1
16
Mod add
16
Register
12
Transistor Counts
Module Transistor Count
FSM 300
Mod Calc 2500
Counter 1600
Mod Multiply 15300
Registers 3000
Compare for zero 36
Total 22736
13
Block Area Estimates
Module Area (µm2)
FSM 3000
Mod Calc 3500
Counter 6000
Mod Multiply 75000
Registers 4000
Compare for zero 100
Total 91600
14
Floorplan
Mod Multiplier
Prime Logic
Memory
Mod Adder
FSM
15
Metal Layers

• Local connections, Vdd, Gnd
• Metal 1 Horizontal
• Metal 2 Vertical
• Global Connections, Clk
• Metal 3 Horizontal
• Metal 4 Vertical

16
Whats Next

• Possibly modify design so that prime logic can be
  turned off
• Continue optimizing
• Current code creates a design that is way too big
• Analyze power/size tradeoffs between adders
• Do Schematic Design

17
Questions?